PIC16F628A-E/P Microchip Technology, PIC16F628A-E/P Datasheet - Page 82
![IC MCU FLASH 2KX14 EEPROM 18DIP](/photos/6/76/67657/18-dip_300mil__sml.jpg)
PIC16F628A-E/P
Manufacturer Part Number
PIC16F628A-E/P
Description
IC MCU FLASH 2KX14 EEPROM 18DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F627A-IP.pdf
(180 pages)
2.PIC16F627A-IP.pdf
(22 pages)
3.PIC16F627A-ISO.pdf
(168 pages)
Specifications of PIC16F628A-E/P
Program Memory Type
FLASH
Program Memory Size
3.5KB (2K x 14)
Package / Case
18-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Eeprom Size
128 x 8
Ram Size
224 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
224 B
Interface Type
SCI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
Data Rom Size
128 B
Height
3.3 mm
Length
22.86 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
3 V
Width
6.35 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3DBF648 - BOARD DAUGHTER ICEPIC3AC162053 - HEADER INTERFACE ICD,ICD2 18DIPACICE0202 - ADAPTER MPLABICE 18P 300 MIL
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
PIC16F627A/628A/648A
FIGURE 12-9:
FIGURE 12-10:
FIGURE 12-11:
DS40044B-page 80
RB1/RX/DT (PIN)
RB1/RX/DT (PIN)
RB1/RX/DT (PIN)
RCV SHIFT REG
RCV BUFFER REG
READ RCV
BUFFER REG
RCREG
RCIF
(INTERRUPT FLAG)
ADEN = 1
(ADDRESS MATCH
Note:
RCV SHIFT
REG
RCV BUFFER REG
READ RCV
BUFFER REG
RCREG
RCIF
(INTERRUPT FLAG)
ADEN = 1
(ADDRESS MATCH
Note:
RCV SHIFT
REG
RCV BUFFER REG
READ RCV
BUFFER REG
RCREG
RCIF
(INTERRUPT FLAG)
ADEN
(ADDRESS MATCH
ENABLE)
ENABLE)
ENABLE)
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG
(Receive Buffer) because ADEN = 1 and Bit 8 = 0.
This timing diagram shows an address byte followed by an data byte. The data byte is not read into the RCREG
(receive buffer) because ADEN was not updated (still = 1) and Bit 8 = 0.
This timing diagram shows an address byte followed by an data byte. The data byte is read into the RCREG
(Receive Buffer) because ADEN was updated after an address match, and was cleared to a ‘0’, so the contents
of the Receive Shift Register (RSR) are read into the Receive Buffer regardless of the value of Bit 8.
‘1’
‘1’
START
START
START
BIT
BIT
BIT
ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST FOLLOWED BY
VALID DATA BYTE
BIT0
BIT0
BIT0
BIT8 = 1, ADDRESS BYTE
BIT8 = 1, ADDRESS BYTE
BIT1
BIT8 = 0, DATA BYTE
BIT1
BIT1
BIT8
BIT8
BIT8
Preliminary
STOP
STOP
STOP
BIT
BIT
BIT
WORD 1
RCREG
WORD 1
RCREG
START
START
START
BIT
BIT
BIT
BIT8 = 1, ADDRESS BYTE
BIT0
BIT0
BIT0
BIT8 = 0, DATA BYTE
BIT8 = 0, DATA BYTE
BIT8
BIT8
BIT8
STOP
STOP
STOP
BIT
BIT
BIT
WORD 2
RCREG
WORD 1
RCREG
2004 Microchip Technology Inc.
‘1’
‘1’