ATMEGA48-20MMH Atmel, ATMEGA48-20MMH Datasheet - Page 26
![MCU AVR 4KB FLASH 20MHZ 28QFN](/photos/12/32/123209/28m1-vqfn_sml.jpg)
ATMEGA48-20MMH
Manufacturer Part Number
ATMEGA48-20MMH
Description
MCU AVR 4KB FLASH 20MHZ 28QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA48-20MMH
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
ATMEGA48x
Core
AVR8
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Data Bus Width
8 bit
Maximum Clock Frequency
16 MHz
Operating Supply Voltage
2.7 V to 5.5 V
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8. System Clock and Clock Options
8.1
8.1.1
8.1.2
8.1.3
26
Clock Systems and their Distribution
ATmega48/88/168
CPU Clock – clk
I/O Clock – clk
Flash Clock – clk
I/O
Figure 8-1
need not be active at a given time. In order to reduce power consumption, the clocks to modules
not being used can be halted by using different sleep modes, as described in
ment and Sleep Modes” on page
Figure 8-1.
The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.
The I/O clock is also used by the External Interrupt module, but note that some external inter-
rupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O
clock is halted. Also note that start condition detection in the USI module is carried out asynchro-
nously when clk
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-
taneously with the CPU clock.
CPU
FLASH
Asynchronous
Timer/Counter
Timer/Counter
Oscillator
presents the principal clock systems in the AVR and their distribution. All of the clocks
Clock Distribution
I/O
is halted, TWI address recognition in all sleep modes.
General I/O
Modules
External Clock
clk
clk
ASY
I/O
38. The clock systems are detailed below.
System Clock
Control Unit
AVR Clock
Multiplexer
Prescaler
Clock
ADC
Source clock
clk
Oscillator
ADC
Crystal
CPU Core
clk
clk
Reset Logic
CPU
FLASH
Crystal Oscillator
Watchdog clock
Low-frequency
Watchdog Timer
RAM
Watchdog
Oscillator
Calibrated RC
“Power Manage-
Flash and
EEPROM
Oscillator
2545S–AVR–07/10
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