PIC16HV785-I/P Microchip Technology, PIC16HV785-I/P Datasheet - Page 119

• Manufacturer Part Number: PIC16HV785-I/P
• Description: IC PIC MCU FLASH 2KX14 20DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16HV785-I/P

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Controller Family/series: PIC16HV
• No. Of I/o's: 18
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 128Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Processor Series: PIC16H
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: RS- 232, USB
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120, DM163029
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 14 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162060 - HEADER INTRFC MPLAB ICD2 20PINAC164039 - MODULE SKT PROMATE II 20DIP/SOICACICE0203 - MPLABICE 20P 300 MIL ADAPTER
• Connectivity: -
• Lead Free Status / Rohs Status: Details

15.3
The PIC16F785/HV785 has 11 sources of interrupt:
• External Interrupt RA2/INT
• TMR0 Overflow Interrupt
• PORTA Change Interrupt
• 2 Comparator Interrupts
• A/D Interrupt
• Timer1 Overflow Interrupt
• Timer2 Match Interrupt
• EEPROM Data Write Interrupt
• Fail-Safe Clock Monitor Interrupt
• CCP Interrupt
The Interrupt Control register (INTCON) and Peripheral
Interrupt register (PIR1) record individual interrupt
requests in flag bits. The INTCON register also has
individual and global interrupt enable bits.
A Global Interrupt Enable bit, GIE of the INTCON Reg-
ister enables (if set) all unmasked interrupts, or dis-
ables (if cleared) all interrupts. Individual interrupts can
be disabled through their corresponding enable bits in
INTCON register and PIE1 register. GIE is cleared on
Reset.
The Return from Interrupt instruction,
interrupt routine, as well as sets the GIE bit, which
re-enables unmasked interrupts.
The following interrupt flags are contained in the INT-
CON register:
• INT Pin Interrupt
• PORTA Change Interrupt
• TMR0 Overflow Interrupt
The peripheral interrupt flags are contained in the
special register PIR1. The corresponding interrupt
enable bit is contained in special register PIE1.
The following interrupt flags are contained in the PIR1
register:
• EEPROM Data Write Interrupt
• A/D Interrupt
• 2 Comparator Interrupts
• Timer1 Overflow Interrupt
• Timer2 Match Interrupt
• Fail-Safe Clock Monitor Interrupt
• CCP Interrupt
When an interrupt is serviced:
• The GIE is cleared to disable any further interrupt
• The return address is PUSHed onto the stack
• The PC is loaded with 0004h
© 2008 Microchip Technology Inc.
Interrupts
RETFIE
, exits
For external interrupt events, such as the INT pin or
PORTA change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends upon when the interrupt event occurs (see
Figure 15-8). The latency is the same for one or two-
cycle instructions. Once in the Interrupt Service
Routine, the source(s) of the interrupt can be
determined by polling the interrupt flag bits. The
interrupt flag bit(s) must be cleared in software before
re-enabling interrupts to avoid multiple interrupt
requests.
For
comparators, A/D, Data EEPROM or CCP modules,
refer to the respective peripheral section.
Note 1: Individual interrupt flag bits are set,
additional
PIC16F785/HV785
2: When an instruction that clears the GIE
regardless
corresponding mask bit or the GIE bit.
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The interrupts, which were
ignored, are still pending to be serviced
when the GIE bit is set again.
information
of
the
on
DS41249E-page 117
status
Timer1,
of
Timer2,
their