PIC12CE518-04I/SN Microchip Technology, PIC12CE518-04I/SN Datasheet - Page 70

• Manufacturer Part Number: PIC12CE518-04I/SN
• Description: IC MCU OTP 512X12 W/EE 8SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12CE518-04I/SN

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 768B (512 x 12)
• Program Memory Type: OTP
• Eeprom Size: 16 x 8
• Ram Size: 25 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• For Use With: 309-1046 - ADAPTER 8-SOIC TO 8-DIP309-1045 - ADAPTER 8-SOIC TO 8-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -

PICmicro MID-RANGE MCU FAMILY
4.1
DS31004A-page 4-2
Introduction
The high performance of the PICmicro™ devices can be attributed to a number of architectural
features commonly found in RISC microprocessors. These include:
• Harvard architecture
• Long Word Instructions
• Single Word Instructions
• Single Cycle Instructions
• Instruction Pipelining
• Reduced Instruction Set
• Register File Architecture
• Orthogonal (Symmetric) Instructions
Figure 4-2
Harvard Architecture:
Harvard architecture has the program memory and data memory as separate memories and are
accessed from separate buses. This improves bandwidth over traditional von Neumann architec-
ture in which program and data are fetched from the same memory using the same bus. To exe-
cute an instruction, a von Neumann machine must make one or more (generally more) accesses
across the 8-bit bus to fetch the instruction. Then data may need to be fetched, operated on, and
possibly written. As can be seen from this description, that bus can be extremely conjested. While
with a Harvard architecture, the instruction is fetched in a single instruction cycle (all 14-bits).
While the program memory is being accessed, the data memory is on an independent bus and
can be read and written. These separated buses allow one instruction to execute while the next
instruction is fetched. A comparison of Harvard vs. von-Neumann architectures is shown in
Figure
Figure 4-1: Harvard vs. von Neumann Block Architectures
Long Word Instructions:
Long word instructions have a wider (more bits) instruction bus than the 8-bit Data Memory Bus.
This is possible because the two buses are separate. This further allows instructions to be sized
differently than the 8-bit wide data word which allows a more efficient use of the program mem-
ory, since the program memory width is optimized to the architectural requirements.
Single Word Instructions:
Single Word instruction opcodes are 14-bits wide making it possible to have all single word
instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single
cycle. With single word instructions, the number of words of program memory locations equals
the number of instructions for the device. This means that all locations are valid instructions.
Typically in the von Neumann architecture, most instructions are multi-byte. In general, a device
with 4-KBytes of program memory would allow approximately 2K of instructions. This 2:1 ratio is
generalized and dependent on the application code. Since each instruction may take multiple
bytes, there is no assurance that each location is a valid instruction.
Memory
Data
4-1.
shows a simple core memory bus arrangement for Mid-Range MCU devices.
8
Harvard
CPU
14
Program
Memory
von-Neumann
CPU
1997 Microchip Technology Inc.
8
Program
Memory
Data
and