PIC16F1827-E/P Microchip Technology, PIC16F1827-E/P Datasheet - Page 109

MCU PIC 8BIT 4K FLASH 18-DIP

PIC16F1827-E/P

Manufacturer Part Number
PIC16F1827-E/P
Description
MCU PIC 8BIT 4K FLASH 18-DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr

Specifications of PIC16F1827-E/P

Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
18-DIP (0.300", 7.62mm)
Controller Family/series
PIC16F
No. Of I/o's
16
Eeprom Memory Size
256Byte
Ram Memory Size
384Byte
Cpu Speed
32MHz
No. Of Timers
5
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
I2C, EUSART (SCI), SPI, USB
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
15
Number Of Timers
4 x 8 bit, 1 x 16 bit
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
On-chip Dac
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
11.1.2
To read a data memory location, the user must write the
address to the EEADRL register, clear the EEPGD and
CFGS control bits of the EECON1 register, and then
set control bit RD. The data is available at the very next
cycle, in the EEDATL register; therefore, it can be read
in the next instruction. EEDATL will hold this value until
another read or until it is written to by the user (during
a write operation).
EXAMPLE 11-1:
EXAMPLE 11-2:
© 2009 Microchip Technology Inc.
BANKSEL EEADRL
MOVLW
MOVWF
BCF
BCF
BSF
MOVF
Note:
BANKSEL EEADRL
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BCF
BTFSC
GOTO
BSF
DATA_EE_ADDR ;
EEADRL
EECON1, CFGS ;Deselect Config space
EECON1, EEPGD;Point to DATA memory
EECON1, RD
EEDATL, W
READING THE DATA EEPROM
MEMORY
Data EEPROM can be read regardless of
the setting of the CPD bit.
DATA_EE_ADDR
EEADRL
DATA_EE_DATA
EEDATL
EECON1, CFGS
EECON1, EEPGD
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
EECON1, WREN
EECON1, WR
$-2
DATA EEPROM READ
DATA EEPROM WRITE
;
;Data Memory
;Address to read
;EE Read
;W = EEDATL
;
;
;Data Memory Address to write
;
;Data Memory Value to write
;Deselect Configuration space
;Point to DATA memory
;Enable writes
;Disable INTs.
;
;Write 55h
;
;Write AAh
;Set WR bit to begin write
;Enable interrupts
;Disable writes
;Wait for write to complete
;Done
Preliminary
11.1.3
To write an EEPROM data location, the user must first
write the address to the EEADRL register and the data
to the EEDATL register. Then the user must follow a
specific sequence to initiate the write for each byte.
The write will not initiate if the above sequence is not
followed exactly (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. Interrupts
should be disabled during this code segment.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
PIC16F/LF1826/27
WRITING TO THE DATA EEPROM
MEMORY
DS41391B-page 109

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