PIC16F684-E/SL Microchip Technology, PIC16F684-E/SL Datasheet - Page 34
![IC PIC MCU FLASH 2KX14 14SOIC](/photos/6/59/65933/150-14-soic_sml.jpg)
PIC16F684-E/SL
Manufacturer Part Number
PIC16F684-E/SL
Description
IC PIC MCU FLASH 2KX14 14SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F684-ISL.pdf
(4 pages)
4.PIC16F684-ISL.pdf
(192 pages)
5.PIC16F684-ISL.pdf
(6 pages)
6.PIC16F684-IST.pdf
(164 pages)
Specifications of PIC16F684-E/SL
Program Memory Type
FLASH
Program Memory Size
3.5KB (2K x 14)
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
PIC16F684
4.2
Every PORTA pin on the PIC16F684 has an
interrupt-on-change option and a weak pull-up option.
RA0 has an Ultra Low-Power Wake-up option. The next
three sections describe these functions.
4.2.1
The ANSEL register is used to configure the Input
mode of an I/O pin to analog. Setting the appropriate
ANSEL bit high will cause all digital reads on the pin to
be read as ‘0’ and allow analog functions on the pin to
operate correctly.
The state of the ANSEL bits has no affect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
4.2.2
Each of the PORTA pins, except RA3, has an
individually configurable internal weak pull-up. Control
bits WPUAx enable or disable each pull-up. Refer to
Register 4-4. Each weak pull-up is automatically turned
off when the port pin is configured as an output. The
pull-ups are disabled on a Power-on Reset by the
RAPU bit of the OPTION register). A weak pull-up is
automatically enabled for RA3 when configured as
MCLR and disabled when RA3 is an I/O. There is no
software control of the MCLR pull-up.
REGISTER 4-3:
DS41202F-page 32
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
R/W-1
ANS7
Additional Pin Functions
Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups and
interrupt-on-change, if available. The corresponding TRIS bit must be set to Input mode in order to allow
external control of the voltage on the pin.
ANSEL REGISTER
WEAK PULL-UPS
ANS<7:0>: Analog Select bits
Analog select between analog or digital function on pins AN<7:0>, respectively.
1 = Analog input. Pin is assigned as analog input
0 = Digital I/O. Pin is assigned to port or special function.
R/W-1
ANS6
ANSEL: ANALOG SELECT REGISTER
W = Writable bit
‘1’ = Bit is set
R/W-1
ANS5
R/W-1
ANS4
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-1
4.2.3
Each of the PORTA pins is individually configurable as
an interrupt-on-change pin. Control bits IOCAx enable
or disable the interrupt function for each pin. Refer to
Register 4-5. The interrupt-on-change is disabled on a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTA. The ‘mismatch’ outputs of the last read are
OR’d together to set the PORTA Change Interrupt Flag
bit (RAIF) in the INTCON register (Register 2-3).
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, clears the inter-
rupt by:
a)
b)
A mismatch condition will continue to set flag bit RAIF.
Reading PORTA will end the mismatch condition and
allow flag bit RAIF to be cleared. The latch holding the
last read value is not affected by a MCLR nor
Brown-out Reset. After these resets, the RAIF flag will
continue to be set if a mismatch is present.
ANS3
(1)
Note:
.
Any read or write of PORTA. This will end the
mismatch condition, then,
Clear the flag bit RAIF.
INTERRUPT-ON-CHANGE
If a change on the I/O pin should occur
when any PORTA operation is being
executed, then the RAIF interrupt flag may
not get set.
R/W-1
ANS2
© 2007 Microchip Technology Inc.
x = Bit is unknown
R/W-1
ANS1
R/W-1
ANS0
bit 0