ATTINY13A-MMUR Atmel, ATTINY13A-MMUR Datasheet - Page 81
![MCU AVR 1KB FLASH 20MHZ 10QFN](/photos/12/13/121304/313-10m1_sml.jpg)
ATTINY13A-MMUR
Manufacturer Part Number
ATTINY13A-MMUR
Description
MCU AVR 1KB FLASH 20MHZ 10QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY13A-SSH.pdf
(176 pages)
Specifications of ATTINY13A-MMUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY13A-MMUR
Manufacturer:
TI
Quantity:
4 430
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- Download datasheet (5Mb)
13.2.3
8126E–AVR–07/10
DIDR0 – Digital Input Disable Register 0
• Bits 1:0 – ACIS[1:0]: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator interrupt. The
different settings are shown in
Table 13-2.
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by
clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the
bits are changed.
• Bits 1:0 – AIN1D, AIN0D: AIN[1:0] Digital Input Disable
When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corre-
sponding PIN Register bit will always read as zero when this bit is set. When an analog signal is
applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be writ-
ten logic one to reduce power consumption in the digital input buffer.
Bit
0x14
Read/Write
Initial Value
ACIS1
0
0
1
1
ACIS1/ACIS0 Settings
R
7
–
0
ACIS0
0
1
0
1
6
–
R
0
Interrupt Mode
Comparator Interrupt on Output Toggle.
Reserved
Comparator Interrupt on Falling Output Edge.
Comparator Interrupt on Rising Output Edge.
Table 13-2 on page
ADC0D
R/W
5
0
ADC2D
R/W
4
0
81.
ADC3D
R/W
3
0
ADC1D
R/W
2
0
AIN1D
R/W
1
0
AIN0D
R/W
0
0
DIDR0
81
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