ATTINY13A-MMUR Atmel, ATTINY13A-MMUR Datasheet - Page 80
![MCU AVR 1KB FLASH 20MHZ 10QFN](/photos/12/13/121304/313-10m1_sml.jpg)
ATTINY13A-MMUR
Manufacturer Part Number
ATTINY13A-MMUR
Description
MCU AVR 1KB FLASH 20MHZ 10QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY13A-SSH.pdf
(176 pages)
Specifications of ATTINY13A-MMUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY13A-MMUR
Manufacturer:
TI
Quantity:
4 430
- Current page: 80 of 176
- Download datasheet (5Mb)
13.2
13.2.1
13.2.2
80
Register Description
ATtiny13A
ADCSRB – ADC Control and Status Register
ACSR– Analog Comparator Control and Status Register
• Bit 6 – ACME: Analog Comparator Multiplexer Enable
When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the
ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written
logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed
description of this bit, see
• Bit 7 – ACD: Analog Comparator Disable
When this bit is written logic one, the power to the Analog Comparator is switched off. This bit
can be set at any time to turn off the Analog Comparator. This will reduce power consumption in
Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be
disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is
changed.
• Bit 6 – ACBG: Analog Comparator Bandgap Select
When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog
Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Compar-
ator. When the bandgap reference is used as input to the Analog Comparator, it will take certain
time for the voltage to stabilize. If not stabilized, the first value may give a wrong value.
• Bit 5 – ACO: Analog Comparator Output
The output of the Analog Comparator is synchronized and then directly connected to ACO. The
synchronization introduces a delay of 1 - 2 clock cycles.
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode defined
by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set
and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding inter-
rupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Com-
parator interrupt is activated. When written logic zero, the interrupt is disabled.
• Bit 2 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny13A and will always read as zero.
Bit
0x03
Read/Write
Initial Value
Bit
0x08
Read/Write
Initial Value
ACD
R/W
R
7
0
7
–
0
ACBG
ACME
R/W
R/W
“Analog Comparator Multiplexed Input” on page
6
0
6
0
ACO
N/A
5
R
R
5
–
0
R/W
ACI
4
0
R
4
–
0
ACIE
R/W
3
0
R
3
–
0
ADTS2
R/W
R
2
–
0
2
0
ADTS1
ACIS1
R/W
R/W
1
0
1
0
79.
ADTS0
ACIS0
R/W
R/W
0
0
0
0
8126E–AVR–07/10
ADCSRB
ACSR
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