PIC12F617-I/SN Microchip Technology, PIC12F617-I/SN Datasheet - Page 99

• Manufacturer Part Number: PIC12F617-I/SN
• Description: IC MCU 8BIT 3.5KB FLASH 8SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F617-I/SN

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Controller Family/series: PIC12
• Ram Memory Size: 128Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: SOIC
• Processor Series: PIC12F
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, ICE2000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

11.4.1
In Half-Bridge mode, two pins are used as outputs to
drive push-pull loads. The PWM output signal is output
on the CCP1/P1A pin, while the complementary PWM
output signal is output on the P1B pin (see Figure 11-8).
This mode can be used for Half-Bridge applications, as
shown in Figure 11-9, or for Full-Bridge applications,
where four power switches are being modulated with
two PWM signals.
In Half-Bridge mode, the programmable dead-band delay
can be used to prevent shoot-through current in Half-
Bridge power devices. The value of the PDC<6:0> bits of
the PWM1CON register sets the number of instruction
cycles before the output is driven active. If the value is
greater than the duty cycle, the corresponding output
remains
Section 11.4.6 “Programmable Dead-Band Delay
mode” for more details of the dead-band delay
operations.
FIGURE 11-9:
 2010 Microchip Technology Inc.
Standard Half-Bridge Circuit (“Push-Pull”)
Half-Bridge Output Driving a Full-Bridge Circuit
inactive
HALF-BRIDGE MODE
during
EXAMPLE OF HALF-BRIDGE APPLICATIONS
the
P1A
P1B
PIC12F609/615/617/12HV609/615
entire
cycle.
P1A
P1B
FET
Driver
FET
Driver
See
FET
Driver
FET
Driver
Since the P1A and P1B outputs are multiplexed with
the PORT data latches, the associated TRIS bits must
be cleared to configure P1A and P1B as outputs.
FIGURE 11-8:
P1A
P1B
td = Dead-Band Delay
Note 1: At this time, the TMR2 register is equal to the
Load
V+
(2)
(2)
2: Output signals are shown as active-high.
(1)
td
PR2 register.
Pulse Width
Load
Period
td
FET
Driver
FET
Driver
EXAMPLE OF HALF-
BRIDGE PWM OUTPUT
+
-
+
-
(1)
DS41302D-page 99
Period
(1)