ATTINY5-TSHR Atmel, ATTINY5-TSHR Datasheet - Page 91

• Manufacturer Part Number: ATTINY5-TSHR
• Description: IC MCU AVR 512B FLASH SOT-23-6
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY5-TSHR

• Package / Case: SOT-23-6
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 12MHz
• Number Of I /o: 4
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 32 x 8
• Program Memory Size: 512B (512 x 8)
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Peripherals: POR, PWM, WDT
• Core Size: 8-Bit
• Controller Family/series: ATtiny
• No. Of I/o's: 4
• Ram Memory Size: 32Byte
• Cpu Speed: 12MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Processor Series: ATTINY5x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 32 B
• Interface Type: ISP
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 4
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

13.9
13.10 ADC Accuracy Definitions
8127D–AVR–02/10
Noise Canceling Techniques
Digital circuitry inside and outside the device generates EMI which might affect the accuracy of
analog measurements. When conversion accuracy is critical, the noise level can be reduced by
applying the following techniques:
Where high ADC accuracy is required it is recommended to use ADC Noise Reduction Mode, as
described in
bypass capacitors does reduce the need for using ADC Noise Reduction Mode
An n-bit single-ended ADC converts a voltage linearly between GND and V
(LSBs). The lowest code is read as 0, and the highest code is read as 2
Several parameters describe the deviation from the ideal behavior:
Figure 13-9. Offset Error
• Keep analog signal paths as short as possible.
• Make sure analog tracks run over the analog ground plane.
• Keep analog tracks well away from high-speed switching digital tracks.
• If any port pin is used as a digital output, it mustn’t switch while a conversion is in progress.
• Place bypass capacitors as close to V
• Offset: The deviation of the first transition (0x00 to 0x01) compared to the ideal transition (at
0.5 LSB). Ideal value: 0 LSB.
Output Code
Section 13.7 on page
Offset
Error
89. A good system design with properly placed, external
CC
and GND pins as possible.
V
REF
ATtiny4/5/9/10
Input Voltage
n
-1.
Ideal ADC
Actual ADC
REF
in 2
n
steps
91