M30624FGAFP#U5 Renesas Electronics America, M30624FGAFP#U5 Datasheet - Page 45
![IC M16C MCU FLASH 100QFP](/photos/12/31/123149/m30624fgafp_u5_sml.jpg)
M30624FGAFP#U5
Manufacturer Part Number
M30624FGAFP#U5
Description
IC M16C MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.M30622SAFPU5.pdf
(277 pages)
2.M30622SAFPU5.pdf
(617 pages)
3.M30622SAFPU5.pdf
(308 pages)
4.M30624FGAFPU5.pdf
(275 pages)
Specifications of M30624FGAFP#U5
Core Processor
M16C/60
Core Size
16-Bit
Speed
16MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-QFP
Cpu Family
M16C
Device Core Size
16/32Bit
Frequency (max)
16MHz
Interface Type
SIM/UART
Total Internal Ram Size
20KB
# I/os (max)
87
Number Of Timers - General Purpose
11
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.2V
On-chip Adc
10-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
-20C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
PQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30624FGAFP#U5M30624FGAFP#D3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30624FGAFP#U5M30624FGAFP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- M30622SAFPU5 PDF datasheet
- M30622SAFPU5 PDF datasheet #2
- M30622SAFPU5 PDF datasheet #3
- M30624FGAFPU5 PDF datasheet #4
- Current page: 45 of 308
- Download datasheet (2Mb)
2.4 Special Instruction Addressing
Chapter 2 Addressing Modes
dsp:20[A0]
dsp:20[A1]
[A1A0]
20-bit absolute
abs20
Address register relative with
20-bit displacement
32-bit address register indirect
The address indicated by displacement
(dsp) plus the content of address register
(A0/A1)—added not including the sign
bits—constitutes the effective address to
be operated on.
However, if the addition resulted in exceed-
ing FFFFF
ignored, and the address returns to
00000
This addressing can be used in LDE, STE,
JMPI, and JSRI instructions.
The following lists the addressing mode and
instruction combinations that can be used.
dsp:20[A0]
dsp:20[A1]
The value indicated by abs20 constitutes
the effective address to be operated on.
The effective address range is 00000
FFFFF
This addressing can be used in LDE, STE,
JSR, and JMP instructions.
The address indicated by 32 concat-
enated bits of address registers (A0
and A1) constitutes the effective
address to be operated on.
However, if the concatenated register
value exceeds FFFFF
above bit 21 are ignored.
This addressing can be used in LDE
and STE instructions.
16
16
.
.
LDE, STE, JMPI, and JSRI in-
structions
JMPI and JSRI instructions
16
, the bits above bit 21 are
16
, the bits
16
to
27
A0 / A1
LDE, STE instructions
JMPI, JSRI instructions
b31
A0
address-H
A1
abs20
Register
address
Register
address
Register
PC
2.4 Special Instruction Addressing
address
b16 b15
address-L
Memory
dsp
dsp
Memory
A0
b0
Memory
Memory
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