M30624FGAFP#U5 Renesas Electronics America, M30624FGAFP#U5 Datasheet - Page 285
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M30624FGAFP#U5
Manufacturer Part Number
M30624FGAFP#U5
Description
IC M16C MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.M30622SAFPU5.pdf
(277 pages)
2.M30622SAFPU5.pdf
(617 pages)
3.M30622SAFPU5.pdf
(308 pages)
4.M30624FGAFPU5.pdf
(275 pages)
Specifications of M30624FGAFP#U5
Core Processor
M16C/60
Core Size
16-Bit
Speed
16MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-QFP
Cpu Family
M16C
Device Core Size
16/32Bit
Frequency (max)
16MHz
Interface Type
SIM/UART
Total Internal Ram Size
20KB
# I/os (max)
87
Number Of Timers - General Purpose
11
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.2V
On-chip Adc
10-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
-20C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
PQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30624FGAFP#U5M30624FGAFP#D3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30624FGAFP#U5M30624FGAFP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
6
Figure 6.1.1. When executing a register transfer instruction starting from an even address
Figure 6.1.2. When executing a register transfer instruction starting from an odd address
Instructions
under execution
Fetch code
Instruction
queue buffer
BCLK
Address bus
Data bus (H)
Data bus (L)
RD
WR
Instructions
under execution
Fetch code
Instruction
queue buffer
BCLK
Address bus
Data bus(H)
Data bus(L)
RD
WR
Content at jump address is
prefetched at the same time
the instruction queue buffer
is cleared.
P : Indicates a prefetch (reading from memory into the instruction queue buffer).
: Indicates the locations of the instruction queue buffer that are cleared.
P : Indicates a prefetch (reading from memory into the instruction queue buffer).
:Indicates the locations of the instruction queue buffer that are cleared.
Content at jump address is
prefetched at the same time the
instruction queue buffer is
cleared.
(Program area: 16-bit bus without wait state; Data area: 16-bit bus without wait state)
(Program area: 16-bit bus without wait state; Data area: 16-bit bus without wait state)
65
04
04
04
64
04
04
04
FC0C4
04
04
04
Jump address
Jump address
FC052
04
04
04
JMP
JMP
04
04
04
Not all codes are ready in
the instruction queue buffer,
so the next read is
performed
04
04
04
TEST_11
TEST_11
FC0C9
73
73
FC056
P
73
73
73
01
01
73
P
73
01
64
FC0CA
FC058
64
01
P
73
01
64
04
04
64
P
73
01
64
Fetch
7301
Fetch
64
04
04
04
MOV.W
04
04
P
7301
64
04
04
MOV.W
FC0CC
04
04
P
04
64
04
04
FC05A
64
04
04
Fetch
Fetch
64
04
04
04
64
04
04
04
04
04
04
P
Content at jump address is
prefetched at the same time
the instruction queue buffer is
cleared.
04
04
04
267
JMP
FC0CE
04
04
04
04
TEST_12
04
04
04
JMP
04
04
04
04
FC05E
TEST_12
73
F1
FC0D1
73
F1
P
73
Content at jump address is
prefetched at the same time the
instruction queue buffer is
cleared.
P
73
FC060
00
73
F1
40
00
P
F1
73
00
40
FC0D2
00
F1
P
Not all codes are ready in the
instruction queue buffer, so the
next read is performed
73
F1
00
Calculation number of cycles
Sample program
Address
FC050
FC051
FC052
FC053
FC054
FC055
FC056
FC056
FC058
FC059
FC05A
FC05B
FC05C
FC05D
FC05E
Sample program
Address
FC0C2
FC0C3
FC0C4
FC0C5
FC0C6
FC0C7
FC0C8
FC0C9
FC0C9
FC0CB
FC0CC
FC0CD
FC0CE
FC0CF
FC0D0
FC0D1
Code
64
04
04
04
04
04
7301
64
04
04
04
04
04
TEST_11:
TEST_12:
Code
65
04
04
04
04
04
04
7301
64
04
04
04
04
04
6.1 Instruction queue buffer
TEST_11:
TEST_12:
Instruction
JMP
NOP
NOP
NOP
NOP
NOP
MOV.W
JMP
NOP
NOP
NOP
NOP
NOP
Instruction
JMP
NOP
NOP
NOP
NOP
NOP
NOP
MOV.W
JMP
NOP
NOP
NOP
NOP
NOP
TEST_11
R0,R1
TEST_12
TEST_11
TEST_12
R0,R1