MCF5474VR200 Freescale Semiconductor, MCF5474VR200 Datasheet - Page 15

• Manufacturer Part Number: MCF5474VR200
• Description: IC MPU 32BIT COLDF 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF547xr

Specifications of MCF5474VR200

• Core Processor: Coldfire V4E
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 99
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.43 V ~ 1.58 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 388-BGA
• Processor Series: MCF547x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Development Tools By Supplier: M5475EVBE
• Maximum Clock Frequency: 83 MHz
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Data Ram Size: 32 KB
• Minimum Operating Temperature: 0 C
• Program Memory Size: 64KB
• Cpu Speed: 200MHz
• Embedded Interface Type: I2C, UART, DMA
• Digital Ic Case Style: BGA
• No. Of Pins: 388
• Rohs Compliant: Yes
• For Use With: M5475EVBGHS - KIT DEV GHS FOR M5475EVBM5474GFE - MODULE M5474 FIRE ENGINEM5474LITEKIT - KIT DEV FOR MCF547X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9
The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports standard SDRAM or
double data rate (DDR) SDRAM, but it does not support both at the same time. The SDRAM controller uses SSTL2 and SSTL3
I/O drivers. Both SSTL drive modes are programmable for Class I or Class II drive strength.
9.1
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the memory bus clock,
when operating in SDR mode on write cycles and relative to SDR_DQS on read cycles. The MCF54
a DDR controller that has an SDR mode. Because it is designed to support DDR, a DQS pulse must be supplied to the MCF54
for each data beat of an SDR read. The MCF54
Care must be taken during board design to adhere to the following guidelines and specs with regard to the SDR_DQS signal
and its usage.
Freescale Semiconductor
SDRAM Bus
SDR SDRAM AC Timing Characteristics
FBCSn, BE/BWEn
TSIZ[1:0]
AD[31:Y]
AD[X:0]
CLKIN
R/W
ALE
OE
TA
MCF547x ColdFire
Figure 12. FlexBus Write Timing
FB1
A[31:Y]
7
FB2
x accomplishes this by asserting a signal called SDR_DQS during read cycles.
FB6
®
Microprocessor, Rev. 4
TSIZ[1:0]
A[X:0]
DATA
FB7
FB3
FB3
7
x SDRAM controller is
SDRAM Bus
7
15
x