M30855FJGP#U3 Renesas Electronics America, M30855FJGP#U3 Datasheet - Page 540

• Manufacturer Part Number: M30855FJGP#U3
• Description: IC M32C MCU FLASH 512K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30855FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 121
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.
REVISION HISTORY
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96
• 9.5.2.2 Entering Wait Mode Description modified
• Figure 9.14 Status Transition Note 4 repleaced to note 5
• 9.6 System Clock Protection Function Description modified
Interrupt
• Table 11.2 Relocatable Vector Table Fault Error deleted; Note 4 deleted
• Figure 11.10 IFSR Register IFSR6 and IFSR7 bit functions changed
• Figure 11.11 Key Input Interrupt Diagram modified
Watchdog Timer
• Chapter description modified
Timer
• Table 15.3 Timer Mode Specifications Write to Timer specification changed
• Table 15.4 Event Counter Mode Specifications Write to Timer specification
• Table 15.5 Event Counter Mode Specifications Write to Timer specification
• Table 15.7 Pulse Width Modulation Mode Specifications Write to Timer
• Figure 15.13 TA0MR to TA4MR Registers Value after reset modified
• Table 15.9 Timer Mode Specifications Write to Timer specification changed
• Table 15.10 Event Counter Mode Specifications Write to Timer specification
• Figure 15.21 TB0MR to TB5MR Registers TCK1 bit name modified
• Figure 15.22 TB0MR to TB5MR Registers Notes 1 and 2 modified
Serial I/O
• Figure 17.1 UARTi Block Diagram Diagram modified
• Figure 17.3 U0MR to U4MR Registers Value after reset modified
• Figure 17.4 U0C0 to U4C0 Registers Note 1 modified
• Figure 17.5 U0C1 to U4C1 Registers Note 2 modified
• Figure 17.9 IFSR Register IFSR6 and IFSR7 bit functions changed
• Table 17.13 Register Settings in I
• 17.3.6 SDA Input The IICM bit in the description modified to the IICM2 bit
• Table 17.19 Special Mode 2 Specifications Transmit/Receive Control speci-
• Table 17.20 Register Settings in Special Mode 2 The IFSR6 register and its
• 17.4.1.2 When Setting the DINC Bit to "0" (Master Mode) Description Modified
• Figure 17.29 SIM Interface Operation Diagram modified
• Figure 17.31 Parity Error Signal Output Timing (LSB First) Diagram modified
changed
changed
specification changed
changed
fication changed; Transmit Start Condision specification changed; Error Detec-
tion specification changed
function deleted
M32C/85 Group(M32C/85, M32C/85T) Hardware Manual
C-21
Description
2
Summary
C Mode SWC and ALS bit functions modified