DF2378BVFQ35V Renesas Electronics America, DF2378BVFQ35V Datasheet - Page 184

IC H8S/2378 MCU FLASH 144-LQFP

DF2378BVFQ35V

Manufacturer Part Number
DF2378BVFQ35V
Description
IC H8S/2378 MCU FLASH 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of DF2378BVFQ35V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
35MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2378BVFQ35V
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2378BVFQ35V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 5 Interrupt Controller
5.3.5
ISR is an IRQ15 to IRQ0 interrupt request flag register.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Note:
Rev.7.00 Mar. 18, 2009 page 116 of 1136
REJ09B0109-0700
Bit Name
IRQ15F
IRQ14F
IRQ13F
IRQ12F
IRQ11F
IRQ10F
IRQ9F
IRQ8F
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
* Only 0 can be written, to clear the flag.
IRQ Status Register (ISR)
Initial Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
Description
[Setting condition]
When the interrupt source selected by ISCR occurs
[Clearing conditions]
Cleared by reading IRQnF flag when IRQnF =
1, then writing 0 to IRQnF flag
When interrupt exception handling is executed
when low-level detection is set and IRQn input
is high
When IRQn interrupt exception handling is
executed when falling, rising, or both-edge
detection is set
When the DTC is activated by an IRQn
interrupt, and the DISEL bit in MRB of the DTC
is cleared to 0
(n = 15 to 0)

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