D13002F16V Renesas Electronics America, D13002F16V Datasheet - Page 276
D13002F16V
Manufacturer Part Number
D13002F16V
Description
IC H8/3002 ROMLESS 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13002F16V.pdf
(702 pages)
Specifications of D13002F16V
Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
38
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D13002F16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select
input or output for each pin in port A.
A pin in port A becomes an output pin if the corresponding PADDR bit is set to 1, and an input
pin if this bit is cleared to 0. In modes 3and 4, PA
the PA7DDR setting.
PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PADDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. If a PADDR bit is set to 1, the corresponding pin maintains its output
state in software standby mode.
Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores data for
pins PA
When a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is
returned directly. When a bit in PADDR is cleared to 0, if port A is read the corresponding pin
level is read.
PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
7
to PA
0
.
R/W
PA
R/W
PA
0
7
0
7
7
7
PA
R/W
R/W
PA
0
6
0
6
6
6
R/W
PA
R/W
PA
0
5
0
5
5
5
Port A data direction 7 to 0
These bits select input or output for port A pins
Port A data 7 to 0
These bits store data for port A pins
260
PA
R/W
PA
R/W
7
0
4
0
4
functions as an address output pin regardless of
4
4
R/W
PA
R/W
PA
0
3
0
3
3
3
R/W
PA
R/W
PA
0
2
0
2
2
2
R/W
PA
R/W
PA
0
1
0
1
1
1
PA
R/W
PA
R/W
0
0
0
0
0
0
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