D13002F16V Renesas Electronics America, D13002F16V Datasheet - Page 117
D13002F16V
Manufacturer Part Number
D13002F16V
Description
IC H8/3002 ROMLESS 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.D13002F16V.pdf
(702 pages)
Specifications of D13002F16V
Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
38
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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Manufacturer
Quantity
Price
Company:
Part Number:
D13002F16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(2) When the IRQaF flag is cleared, there is contention with IRQb generation (IRQaF flag
If the above setting conditions (1) to (3) and generation conditions (1) and (3) are all fulfilled,
when the ISR write in generation condition (2) is performed the IRQbF flag will be cleared
inadvertently, and interrupt exception handling will not be executed.
However, this inadvertent clearing of the IRQbF flag will not occur if 0 is written to this flag even
once between generation conditions (1) and (2).
Either of the methods shown below should be used to prevent this problem.
Method 1
When clearing the IRQaF flag, read ISR as a byte unit instead of using a bit-manipulation
instruction, and write a byte value that clears the IRQaF flag to 0 and sets the other bits to 1.
Example: When a = 0
IRQbF flag is cleared by the execution of interrupt exception handling.
setting). (IRQbF was 0 when ISR was read to clear the IRQaF flag, but IRQbF is set to 1
before ISR is written to.)
Figure 5-9 IRQnF Flag when Interrupt Exception Handling is not Executed
MOV.B @ISR, R0L
MOV.B #HFE, R0L
MOV.B R0L, @ISR
IRQaF
IRQbF
TIER write cycle by CPU
Generation condition (1)
1 read 0 written
1 read
written
0
100
IRQb
executed
IMIA exception handling
Generation condition (2)
(Inadvertent clearing)
1 read 0 written
1 read 0 written
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