C8051F704-GM Silicon Laboratories Inc, C8051F704-GM Datasheet - Page 223
![IC 8051 MCU 15K FLASH 48-QFN](/photos/12/27/122740/c8051f704-gm_sml.jpg)
C8051F704-GM
Manufacturer Part Number
C8051F704-GM
Description
IC 8051 MCU 15K FLASH 48-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F70xr
Specifications of C8051F704-GM
Program Memory Type
FLASH
Program Memory Size
15KB (15K x 8)
Package / Case
48-QFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Cap Sense, POR, PWM, Temp Sensor, WDT
Number Of I /o
39
Eeprom Size
32 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F7x
Core
8051
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
39
Number Of Timers
4 x 16 bit
Operating Supply Voltage
1.8 V to 3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F700DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1635 - DEV KIT FOR C8051F700
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1610-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F704-GM
Manufacturer:
Silicon Laboratories Inc
Quantity:
135
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The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as defined in Equation 30.1.The selected
clock source may be shared by other peripherals so long as the timer is left running at all times. For exam-
ple, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer configuration
is covered in Section “33. Timers” on page 262.
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 30.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approximated by Equation 30.2.
Figure 30.4 shows the typical SCL generation described by Equation 30.2. Notice that T
twice as large as T
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by equation Equation 30.1.
Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA
setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high.
The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable
after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times
meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 30.2 shows the min-
Timer Source
Overflows
SCL
LOW
T
Equation 30.1. Minimum SCL High and Low Times
. The actual SCL output may vary due to other devices on the bus (SCL may be
Low
SMBCS1
T
Figure 30.4. Typical SMBus SCL Generation
Table 30.1. SMBus Clock Source Selection
HighMin
0
0
1
1
Equation 30.2. Typical SMBus Bit Rate
BitRate
SMBCS0
=
T
High
T
0
1
0
1
LowMin
=
f
--------------------------------------------- -
ClockSourceOverflow
Rev. 1.0
Timer 2 High Byte Overflow
=
Timer 2 Low Byte Overflow
SMBus Clock Source
--------------------------------------------- -
f
ClockSourceOverflow
Timer 0 Overflow
Timer 1 Overflow
3
1
SCL High Timeout
C8051F70x/71x
HIGH
is typically
223
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