C8051F704-GM Silicon Laboratories Inc, C8051F704-GM Datasheet - Page 166
C8051F704-GM
Manufacturer Part Number
C8051F704-GM
Description
IC 8051 MCU 15K FLASH 48-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F70xr
Specifications of C8051F704-GM
Program Memory Type
FLASH
Program Memory Size
15KB (15K x 8)
Package / Case
48-QFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Cap Sense, POR, PWM, Temp Sensor, WDT
Number Of I /o
39
Eeprom Size
32 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F7x
Core
8051
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
39
Number Of Timers
4 x 16 bit
Operating Supply Voltage
1.8 V to 3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F700DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1635 - DEV KIT FOR C8051F700
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1610-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F704-GM
Manufacturer:
Silicon Laboratories Inc
Quantity:
135
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C8051F70x/71x
SFR Definition 25.1. VDM0CN: V
SFR Address = 0xFF; SFR Page = All Pages
25.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Section “9. Electrical Characteristics”
on page 47 for complete RST pin specifications. The PINRSF flag (RSTSRC.0) is set on exit from an exter-
nal reset.
25.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than the MCD timeout, the one-shot will time out and generate a reset.
After a MCD reset, the MCDRSF flag (RSTSRC.2) will read 1, signifying the MCD as the reset source; oth-
erwise, this bit reads 0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 dis-
ables it. The state of the RST pin is unaffected by this reset.
166
Name
Reset
5:0
Bit
Type
7
6
Bit
VDDSTAT
VDMEN
Unused
VDMEN
Name
Varies
R/W
7
VDDSTAT
V
This bit turns the V
tem resets until it is also selected as a reset source in register RSTSRC (SFR Def-
inition 25.2). Selecting the V
may generate a system reset. In systems where this reset would be undesirable, a
delay should be introduced between enabling the V
reset source.
0: V
1: V
V
This bit indicates the current power supply status (V
0: V
1: V
Read = Varies; Write = Don’t care.
Varies
DD
DD
R
6
DD
DD
DD
DD
Monitor Enable.
Status.
Monitor Disabled.
Monitor Enabled.
is at or below the V
is above the V
Varies
R
5
DD
DD
DD
monitor circuit on/off. The V
Monitor Control
monitor threshold.
Varies
Rev. 1.0
DD
R
4
DD
monitor threshold.
monitor as a reset source before it has stabilized
Function
Varies
R
3
Varies
DD
R
2
DD
DD
Monitor cannot generate sys-
Monitor and selecting it as a
Monitor output).
Varies
R
1
Varies
R
0
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