C8051F339-GM Silicon Laboratories Inc, C8051F339-GM Datasheet - Page 137

• Manufacturer Part Number: C8051F339-GM
• Description: IC MCU 16K FLASH 24QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F33xr

Specifications of C8051F339-GM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-QFN
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F336DK
• Minimum Operating Temperature: - 40 C
• Package: 24QFN EP
• Device Core: 8051
• Family Name: C8051F33x
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1426-5

SFR Definition 20.17. P2MDOUT: Port 2 Output Mode
SFR Address = 0xA6
SFR Definition 20.18. P2SKIP: Port 2 Skip
SFR Address = 0xD6
Note: P2.0 is not available for analog input in the QFN20-packaged devices, and P2.1-P2.4 are only available in the
Note: P2.0 is not available for crossbar peripherals in the QFN20-packaged devices, and P2.1-P2.4 are only
Name
Reset
Name
Reset
Bit
7:5
4:0 P2MDOUT[4:0] Output Configuration Bits for P2.4–P2.0 (respectively).
Bit
7:4
3:0
Type
Type
Bit
Bit
QFN24-packaged devices.
available in the QFN24-packaged devices.
P2SKIP[3:0]
UNUSED
UNUSED
Name
Name
R
R
7
0
7
0
Unused. Read = 000b; Write = Don’t Care
These bits are ignored if the corresponding bit in register P2MDIN is logic 0.
0: Corresponding P2.n Output is open-drain.
1: Corresponding P2.n Output is push-pull.
Unused. Read = 0000b; Write = Don’t Care
Port 2 Crossbar Skip Enable Bits.
These bits select Port 2 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P2.n pin is not skipped by the Crossbar.
1: Corresponding P2.n pin is skipped by the Crossbar.
R
R
6
0
6
0
R
R
5
0
5
0
Rev.1.0
R
4
0
4
0
Function
Function
3
0
3
0
P2MDOUT[4:0]
C8051F336/7/8/9
R/W
2
0
2
0
P2SKIP[7:0]
R/W
1
0
1
0
0
0
0
0
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