ST10R167-Q3 STMicroelectronics, ST10R167-Q3 Datasheet - Page 43

• Manufacturer Part Number: ST10R167-Q3
• Description: IC MCU 16BIT ROMLESS 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10R167-Q3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-QFP
• Processor Series: ST10R1x
• Core: ST10
• Data Bus Width: 16 bit
• Program Memory Size: 32 KB
• Data Ram Size: 4 KB
• Interface Type: CAN/SSC/USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-2043

XX - ELECTRICAL CHARACTERISTICS (continued)
XX.4.3 - Prescaler operation
When pins P0.15-13 (P0H.7-5) equal ’001’ during
reset the CPU clock is derived from the internal
oscillator (input clock signal) by a 2:1 prescaler.
The frequency of f
f
duration of an individual TCL) is defined by the
period of the input clock f
The timings listed in the AC Characteristics that
refer to TCLs, therefore, can be calculated using
the period of f
Note that if the bit OWDDIS in SYSCON register
is cleared, the PLL is running on its free-running
frequency and delivers the clock signal for the
Oscillator Watchdog. If bit OWDDIS is set, then
the PLL is switched off.
XX.4.4 - Direct drive
When pins P0.15-13 (P0H.7-5) equal ’011’ during
reset the on-chip phase locked loop is disabled and
the CPU clock is directly driven from the internal
oscillator with the input clock signal.
The frequency of f
frequency of f
f
defined by the duty cycle of the input clock f
The timings listed below that refer to TCL
therefore must be calculated using the minimum
TCL that is possible under the respective
circumstances. This minimum value can be
calculated by the following formula:
For two consecutive TCLs the deviation caused
by the duty cycle of f
duration of 2TCL is always 1/f
value TCL
for timings that require an odd number of TCLs
(1,3,...). Timings that require an even number of
TCLs (2,4,...) may use the formula:
Note The address float timings in Multiplexed
Note that if the bit OWDDIS in SYSCON register
is cleared, the PLL is running on its free-running
frequency and delivers the clock signal for the
Oscillator Watchdog. If bit OWDDIS is set, then
the PLL is switched off.
XTAL
CPU
(i.e. the duration of an individual TCL) is
and the high and low time of f
bus mode (t
duration of TCL (TCL
instead of TCL
min
TCL m in
XTAL
therefore has to be used only once
XTAL
2TCL
DC
for any TCL.
11
CPU
so the high and low time of
=
=
min
XTAL
=
and t
1 f XTAL *DC m in
duty cycle
CPU
1 f XTAL
.
is half the frequency of
XTAL
is compensated so the
45
max
directly follows the
) use the maximum
.
XTAL
= 1/f
. The minimum
XTAL
CPU
x DC
(i.e. the
XTAL
max
.
)
XX.4.5 - Oscillator watchdog (OWD)
When the clock option selected is direct drive or
direct drive with prescaler, in order to provide a fail
safe mechanism in case of a loss of the external
clock, an oscillator watchdog is implemented as
an additional functionality of the PLL circuitry. This
oscillator watchdog operates as follows :
After a reset, the Oscillator Watchdog is enabled
by default. To disable the OWD, the bit OWDDIS
(bit 4 of SYSCON register) must be set.
When the OWD is enabled, the PLL is running on
its free-running frequency, and increment the
Oscillator Watchdog counter. On each transition
of XTAL1 pin, the Oscillator Watchdog is cleared.
If an external clock failure occurs, then the
Oscillator Watchdog counter overflows (after 16
PLL clock cycles).
The CPU clock signal will be switched to the PLL
free-running clock signal, and the Oscillator
Watchdog Interrupt Request (XP3INT) is flagged.
The CPU clock will not switch back to the external
clock even if a valid external clock exits on XTAL1
pin. Only a hardware reset can switch the CPU
clock source back to direct clock input.
When the OWD is disabled, the CPU clock is
always fed from the oscillator input and the PLL is
switched off to decrease power supply current.
XX.4.6 - Phase locked loop
For all other combinations of pins P0.15-13
(P0H.7-5) during reset the on-chip phase locked
loop is enabled and provides the CPU clock (see
table above). The PLL multiplies the input
frequency by the factor F which is selected via the
combination of pins P0.15-13 (i.e. f
F). With every F’th transition of f
circuit synchronizes the CPU clock to the input
clock. This synchronization is done smoothly, i.e.
the CPU clock frequency does not change
abruptly.
Due to this adaptation to the input clock the
frequency of f
locked to f
of f
individual TCLs.
The timings listed in the AC Characteristics that
refer to TCL therefore must be calculated using
the minimum TCL that is possible under the
respective circumstances.
CPU
which also effects the duration of
XTAL
CPU
. The slight variation causes a jitter
is constantly adjusted so it is
XTAL
CPU
ST10R167
= f
the PLL
XTAL
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