ST10R167-Q3 STMicroelectronics, ST10R167-Q3 Datasheet - Page 17

• Manufacturer Part Number: ST10R167-Q3
• Description: IC MCU 16BIT ROMLESS 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10R167-Q3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-QFP
• Processor Series: ST10R1x
• Core: ST10
• Data Bus Width: 16 bit
• Program Memory Size: 32 KB
• Data Ram Size: 4 KB
• Interface Type: CAN/SSC/USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-2043

VIII - CAPTURE/COMPARE (CAPCOM) UNIT
The ST10R167 has two 16 channel CAPCOM
units. They support generation and control of
timing sequences on up to 32 channels with a
maximum resolution of 320ns at 25MHz CPU
clock. The CAPCOM units are typically used to
handle high speed I/O tasks such as pulse and
waveform generation, pulse width modulation
(PMW), Digital to Analog (D/A) conversion,
software timing, or time recording relative to
external events.
Four 16-bit timers (T0/T1, T7/T8) with reload
registers provide two independent time bases for
the capture/compare register array.
The input clock for the timers is programmable to
several prescaled values of the internal system
clock, or may be derived from an overflow/
underflow of timer T6 in module GPT2. This
provides a wide range of variation for the timer
period
adjustments to application specific requirements.
In addition, external count inputs for CAPCOM
timers T0 and T7 allow event scheduling for the
capture/compare registers relative to external
events.
Each of the two capture/compare register arrays
contain
registers, each of which may be individually
allocated to either CAPCOM timer T0 or T1 (T7 or
T8, respectively), and programmed for capture or
compare functions. Each register has one
associated port pin which serves as an input pin
Table 4 : Compare modes
Table 5 : CAPCOM timer input frequencies, resolution and periods
Mode 0
Mode 1
Mode 2
Mode 3
Double Register Mode
Pre-scaler for f
Input Frequency
Resolution
Period
f
Compare Modes
CPU
= 25MHz
and
16
CPU
resolution
dual
3.125MHz
21.0ms
purpose
320ns
000
Interrupt-only compare mode ; several compare interrupts per timer period are possible
Pin toggles on each compare match ; several compare events per timer period are possible
Interrupt-only compare mode ; only one compare interrupt per timer period is generated
Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow ; only one compare event per
timer period is generated
Two registers operate on one pin; pin toggles on each compare match ; several compare
events per timer period are possible.
8
B
and
1.56MHz
capture/compare
41.9ms
allows
640ns
001
16
B
precise
781KHz
83.9ms
1.28 s
010
32
B
Timer Input Selection TxI
391KHz
for triggering the capture function, or as an output
pin (except for CC24...CC27) to indicate the
occurrence of a compare event.
When a capture/compare register has been
selected for capture mode, the current contents of
the allocated timer will be latched (captured) into
the capture/compare register in response to an
external event at the port pin which is associated
with this register. In addition, a specific interrupt
request for this capture/compare register is
generated. Either a positive, a negative, or both a
positive and a negative external signal transition
at the pin can be selected as the triggering event.
The contents of all registers which have been
selected for one of the five compare modes are
continuously compared with the contents of the
allocated timers. When a match occurs between
the timer value and the value in a capture/
compare register, specific actions will be taken
based on the selected compare mode (see
Table 4).
The input frequencies f
a function of the CPU clocks. The formulas are
detailed in the user manual. The timer input fre-
quencies, resolution and periods which result
from the selected pre-scaler option in TxI when
using a 25MHz CPU clock are listed in the table
below. The numbers for the timer periods are
based on a reload value of 0000
numbers may be rounded to 3 significant figures
(see Table 5).
2.56 s
167ms
011
64
B
Function
195KHz
5.12 s
336ms
100
128
B
97.7KHz
10.24 s
671ms
101
256
Tx
B
for Tx are determined as
48.8KHz
20.48 s
1.34s
H
110
512
. Note that some
B
ST10R167
24.4KHz
40.96 s
2.68s
1024
111
17/63
B