EZ80F91NAA50SG Zilog, EZ80F91NAA50SG Datasheet - Page 61

• Manufacturer Part Number: EZ80F91NAA50SG
• Description: IC ACCLAIM MCU 256KB 144BGA
• Manufacturer: Zilog
• Series: eZ80® AcclaimPlus!™r

Specifications of EZ80F91NAA50SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LBGA
• Processor Series: EZ80F91x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F910300ZCOG, eZ80F910200KITG
• Minimum Operating Temperature: 0 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4566

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PS027001-0707
Mode 7(Input)
Mode 2
Mode 6
Mode 8
Mode 9
System Clock
* Writing to the Px_DR stores
Data
* Reading from the Px_DR returns
Alternate Function Output
the value stored in this register
the value in this register
D
Px_DR*
Figure 6. GPIO Port Pin Block Diagram for Output and Input/Output Mode
Figure 5. GPIO Port Pin Block Diagram for Input and Interrupt Modes
Q
Q
Simplified GPIO Port Block Diagram for Modes 1, 3, 4 and 7 (Output)
Mode 3
Mode 4
Mode 1
Mode 7 (Output)
GPIO Output Buffer
Tristated for
modes 2,6,8,9
and 7(Input)
ENB
SysClock
Default Value
Mode 7(Input)
Clear Interrupt
Modes 6,8,9
D
GPIO Port Pin
Q
GPIO Output Buffer
Px_DR*
D
ENB
Q
General Purpose Input/Output
Product Specification
GPIO Port
Pin
Interrupt
Logic
External Pull-up
(Open source)
eZ80F91 ASSP
Required for
Input to chip
VDD
Mode 4
Alternate
Function
Input
Interrupt
Required for
(open drain)
External
Pull-up
Mode 3
53