EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 40
![IC ARM920T MCU 200MHZ 352-PBGA](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-IBZ
Manufacturer Part Number
EP9312-IBZ
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-IBZ
Core Size
16/32-Bit
Package / Case
352-BGA
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Controller Family/series
(ARM9)
A/d Converter
12 Bits
No. Of I/o Pins
65
Clock Frequency
200MHz
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1260
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9312-IBZ
Manufacturer:
CIRRUS
Quantity:
30
Company:
Part Number:
EP9312-IBZ
Manufacturer:
HITTITE
Quantity:
1 200
EP9312
Universal Platform SOC Processor
40
HSTROBE
HSTROBE
DDMARDYn
DD (15:0)
DD (15:0)
HSTROBE
(device)
(device)
DD (15:0)
DMACKn
DMARQ
(host)
(host)
(device)
(device)
Note:
Note:
STOP
(host)
(host)
(host)
(host)
DD (15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as
cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are
driven by the host.
1. The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than t
2. If the t
negated.
t
DH
t
DVH
SR
timing is not satisfied, the device may receive zero, one, or two more data words from the host.
Figure 26. Device Pausing an Ultra DMA data-out Burst
t
Copyright 2010 Cirrus Logic (All Rights Reserved)
CYCWR
Figure 25. Sustained Ultra DMA data-out Burst
t
DS
t
t
SR
DVS
t
2CYCWR
t
DH
t
DVH
t
CYCWR
t
RFS
t
DS
t
RP
t
DVS
t
DH
t
2CYCWR
t
DVH
RP
after DDMARDYn is
DS515F2