EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 26

IC ARM920T MCU 200MHZ 352-PBGA

EP9312-IBZ

Manufacturer Part Number
EP9312-IBZ
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9312-IBZ

Core Size
16/32-Bit
Package / Case
352-BGA
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Controller Family/series
(ARM9)
A/d Converter
12 Bits
No. Of I/o Pins
65
Clock Frequency
200MHz
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
Other names
598-1260

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9312-IBZ
Manufacturer:
CIRRUS
Quantity:
30
Part Number:
EP9312-IBZ
Manufacturer:
HITTITE
Quantity:
1 200
Part Number:
EP9312-IBZ
Manufacturer:
Cirrus Logic Inc
Quantity:
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EP9312
Universal Platform SOC Processor
Static Memory Burst Write Cycle
26
AD setup to WRn assert time
AD hold from WRn deassert time
WRN/DQMn deassert to AD transition time
CSn hold from WRn deassert time
CSn to WRn assert delay time
CSn to DQMn assert delay time
DQMn assert time
DQMn deassert time
WRn assert time
WRn deassert time
WRn/DQMn deassert to DA transition time
WRn/DQMn assert to DA valid time
DQMn
WAIT
WRn
CSn
AD
RD
DA
Note:
t
DQMd
These characteristics are valid when the Page Mode Enable (Burst Mode) bit is set. See the User's Guide for details.
t
WRd
t
ADs
Parameter
t
DAv
t
t
DQpwL
WRpwL
Figure 13. Static Memory Burst Write Cycle Timing Measurement
t
t
t
ADd
WRpwH
DQpwH
Copyright 2010 Cirrus Logic (All Rights Reserved)
t
DAh
Symbol
t
t
t
t
WRpwH
t
DQpwH
WRpwL
DQpwL
t
DQMd
t
t
t
t
t
t
WRd
ADh
ADd
CSh
DAh
ADs
DAv
t
t
HCLK
HCLK
t
Min
HCLK
7
− 3
× 2
t
t
HCLK
HCLK
× (WST1 + 11)
× (WST1 + 1)
Typ
(t
(t
HCLK
HCLK
t
HCLK
Max
× 2) + 14
2
1
8
× 2) + 7
+ 6
t
ADh
t
CSh
DS515F2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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