EP9315-IB Cirrus Logic Inc, EP9315-IB Datasheet - Page 3
![IC ARM920T MCU 200MHZ 352-PBGA](/photos/12/23/122388/ep9315-ib_sml.jpg)
EP9315-IB
Manufacturer Part Number
EP9315-IB
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9315-IB
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
352-BGA
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1262
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9315-IBZ
Manufacturer:
CIRRUS
Quantity:
13
Company:
Part Number:
EP9315-IBZ
Manufacturer:
CIRRUS
Quantity:
347
HDLC
SDRAM Controller
ER638E2B
Description
When the final byte of a received packet is read into the DMA controller's buffer, the software will be notified
by an HDLC RFC interrupt. However, the DMA controller may not have written the currently buffered part of
the packet to memory, so that the last one to fifteen bytes of a packet may not be accessible.
Workaround
To ensure that the DMA channel empties the buffer, do the following (in the HDLC interrupt handler, for
example):
1) Note the values in the MAXCNTx and REMAIN registers for the DMA channel. The difference is the num-
2) Temporarily disable the UART DMA RX interface by clearing the RXDMAE bit in the UART1DMACtrl reg-
3) Wait until the difference between the CURRENTx and BASEx registers in the DMA channel is equal to
At this point, the rest of the packet is guaranteed to have been written to memory. Using this method will
cause an extra byte to be read from the UART by the DMA channel and also written to memory. This last
byte should be ignored.
Description 1
Using the SDRAM controller in auto-precharge mode will produce system instability at external bus speeds
greater than 50MHz.
Workaround
Do not turn on the auto-precharge feature of the SDRAM controller if the external bus speed will be greater
than 50 MHz.
Description 2
When the SDRAM controller is configured for PRECHARGE ALL command, the actual sequence is not
always issued to the SDRAM device(s).
Workaround
Do a read from each SDRAM bank so that a PRECHARGE command is issued to each bank of the SDRAM
device. This will satisfy the required SDRAM initialization sequence.
Due to the effectiveness and simplicity of the software workaround, no silicon fix is planned.
ber of bytes read from the UART/HDLC, which is the size of the HDLC packet. Call this number N. Note
that the BC field of the UART1HDLCRXInfoBuf register should also be N.
ister.
N + 1.
3