EP9315-IB Cirrus Logic Inc, EP9315-IB Datasheet - Page 11
![IC ARM920T MCU 200MHZ 352-PBGA](/photos/12/23/122388/ep9315-ib_sml.jpg)
EP9315-IB
Manufacturer Part Number
EP9315-IB
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9315-IB
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
352-BGA
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Other names
598-1262
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9315-IBZ
Manufacturer:
CIRRUS
Quantity:
13
Company:
Part Number:
EP9315-IBZ
Manufacturer:
CIRRUS
Quantity:
347
ER638E2B
Note: The effect of branches should also be accounted for, as it is the instruction stream as seen by the
coprocessor that matters, not the order of instructions in the source code. To avoid this error when entering
exception and interrupt handlers, the first seven instruction in an interrupt or exception handler should not
be a coprocessor instructions.
Description 5
When operating in serialized mode
unpredictable amount, but cause no other side effects.
Workaround
One workaround is to avoid these instructions. With this approach, an alternative instruction sequence may
accomplish the shift with the following steps:
Another workaround is to never operate in serialized mode. With this approach, synchronous exceptions are
not possible.
Description 6
If an interrupt occurs during the execution of cfldr32 or cfmv64lr, the instruction may not sign extend the
result correctly.
Either instruction places a 32 bit value into the lower half of one of the coprocessor general purpose registers
c0 through c15 and sign extends the high (32nd) bit through the upper half of the register. If an IRQ or FIQ
to the ARM processor interrupts either of these instructions at the right time, the coprocessor will properly
load the low 32 bits of the target register, but instead of sign extending it will replicate the low 32 bit into the
upper 32 bits. Code that depends on sign extension will fail to operate correctly.
Workaround
Possible workarounds include:
- Move the data to be shifted to ARM register(s)
- Shift the data using non-coprocessor instructions
- Move the shifted data back to the coprocessor.
- Disable interrupts when executing cfldr32 or cfmv64lr instructions.
- Avoid executing these two instructions.
- Do not depend on the sign extension to occur; that is, ignore the upper word in any calculations
- Add extra code to sign extend the lower word after it is loaded by explicitly forcing the upper word
involving data loaded using these instructions.
to be all zeroes or all ones, as appropriate. It is possible to do this selectively in exception or interrupt
handler code. If the instruction preceding the interrupted instruction can be determined, and it is a
cfldr32 or cfmv64lr, the instruction may be re-executed or explicitly sign extended before returning
from interrupt or exception.
2
, cfrshl32 and cfrshl64 do not work properly. The instructions shift by an
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