ATMEGA169L-8MI Atmel, ATMEGA169L-8MI Datasheet - Page 93

• Manufacturer Part Number: ATMEGA169L-8MI
• Description: IC MCU AVR 16K LV 8MHZ IND 64QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA169L-8MI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• For Use With: ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA169L-4MI; ATMEGA169L-4MI

Timer/Counter0 and
Timer/Counter1
Prescalers
Internal Clock Source
Prescaler Reset
External Clock Source
2514H–AVR–05/03
Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the
Timer/Counters can have different prescaler settings. The description below applies to
both Timer/Counter1 and Timer/Counter0.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 =
1). This provides the fastest operation, with a maximum Timer/Counter clock frequency
equal to system clock frequency (f
caler can be used as a clock source. The prescaled clock has a frequency of either
f
The prescaler is free running, i.e., operates independently of the Clock Select logic of
the Timer/Counter, and it is shared by Timer/Counter1 and Timer/Counter0. Since the
prescaler is not affected by the Timer/Counter’s clock select, the state of the prescaler
will have implications for situations where a prescaled clock is used. One example of
prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 >
CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the
first count occurs can be from 1 to N+1 system clock cycles, where N equals the pres-
caler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program
execution. However, care must be taken if the other Timer/Counter that shares the
same prescaler also uses prescaling. A prescaler reset will affect the prescaler period
for all Timer/Counters it is connected to.
An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock
(clk
chronization logic. The synchronized (sampled) signal is then passed through the edge
detector. Figure 37 shows a functional equivalent block diagram of the T1/T0 synchroni-
zation and edge detector logic. The registers are clocked at the positive edge of the
internal system clock (
system clock.
The edge detector generates one clk
ative (CSn2:0 = 6) edge it detects.
Figure 37. T1/T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system
clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T1/T0 has been stable for
at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock
pulse is generated.
Each half period of the external clock applied must be longer than one system clock
cycle to ensure correct sampling. The external clock must be guaranteed to have less
than half the system clock frequency (f
CLK_I/O
Tn
T1
clk
/clk
I/O
/8, f
T0
CLK_I/O
). The T1/T0 pin is sampled once every system clock cycle by the pin syn-
D
LE
/64, f
Q
CLK_I/O
Synchronization
clk
D
I/O
/256, or f
). The latch is transparent in the high period of the internal
Q
CLK_I/O
CLK_I/O
T1
/clk
ExtClk
). Alternatively, one of four taps from the pres-
T
/1024.
0
< f
pulse for each positive (CSn2:0 = 7) or neg-
clk_I/O
/2) given a 50/50% duty cycle. Since
D
ATmega169V/L
Q
Edge Detector
Tn_sync
(To Clock
Select Logic)
93