ATMEGA169L-8MI Atmel, ATMEGA169L-8MI Datasheet - Page 82

• Manufacturer Part Number: ATMEGA169L-8MI
• Description: IC MCU AVR 16K LV 8MHZ IND 64QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA169L-8MI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• For Use With: ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA169L-4MI; ATMEGA169L-4MI

Force Output Compare
Compare Match Blocking by
TCNT0 Write
Using the Output Compare
Unit
82
ATmega169V/L
The OCR0A Register is double buffered when using any of the Pulse Width Modulation
(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation,
the double buffering is disabled. The double buffering synchronizes the update of the
OCR0 Compare Register to either top or bottom of the counting sequence. The synchro-
nization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby
making the output glitch-free.
The OCR0A Register access may seem complex, but this is not case. When the double
buffering is enabled, the CPU has access to the OCR0A Buffer Register, and if double
buffering is disabled the CPU will access the OCR0A directly.
In non-PWM waveform generation modes, the match output of the comparator can be
forced by writing a one to the Force Output Compare (FOC0A) bit. Forcing compare
match will not set the OCF0A Flag or reload/clear the timer, but the OC0A pin will be
updated as if a real compare match had occurred (the COM0A1:0 bits settings define
whether the OC0A pin is set, cleared or toggled).
All CPU write operations to the TCNT0 Register will block any compare match that
occur in the next timer clock cycle, even when the timer is stopped. This feature allows
OCR0A to be initialized to the same value as TCNT0 without triggering an interrupt
when the Timer/Counter clock is enabled.
Since writing TCNT0 in any mode of operation will block all compare matches for one
timer clock cycle, there are risks involved when changing TCNT0 when using the Output
Compare channel, independently of whether the Timer/Counter is running or not. If the
value written to TCNT0 equals the OCR0A value, the compare match will be missed,
resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value
equal to BOTTOM when the counter is downcounting.
The setup of the OC0A should be performed before setting the Data Direction Register
for the port pin to output. The easiest way of setting the OC0A value is to use the Force
Output Compare (FOC0A) strobe bits in Normal mode. The OC0A Register keeps its
value even when changing between Waveform Generation modes.
Be aware that the COM0A1:0 bits are not double buffered together with the compare
value. Changing the COM0A1:0 bits will take effect immediately.
2514H–AVR–05/03