DSPIC30F3012-20I/ML Microchip Technology, DSPIC30F3012-20I/ML Datasheet - Page 57
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DSPIC30F3012-20I/ML
Manufacturer Part Number
DSPIC30F3012-20I/ML
Description
IC DSPIC MCU/DSP 24K 44QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(210 pages)
2.DSPIC30F2011-20ISO.pdf
(6 pages)
3.DSPIC30F3012-20ISO.pdf
(14 pages)
4.DSPIC30F3012-20ISO.pdf
(20 pages)
5.DSPIC30F2011-20IP.pdf
(206 pages)
Specifications of DSPIC30F3012-20I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
24KB (8K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
12
Flash Memory Size
24KB
Supply Voltage Range
2.5V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44QFN5 - SOCKET TRANS ICE 18DIP TO 44QFNAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F301220IML
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F3012-20I/ML
Manufacturer:
Microchip Technology
Quantity:
135
6.3
To write an EEPROM data location, the following
sequence must be followed:
1.
2.
3.
EXAMPLE 6-4:
© 2008 Microchip Technology Inc.
; Point to data memory
; The NVMADR captures last table access address
; Select data EEPROM for 1 word op
; Operate key to allow write operation
; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete
Erase data EEPROM word.
a)
b)
c)
d)
e)
f)
g)
h)
Write data word into data EEPROM write
latches.
Program 1 data word into data EEPROM.
a)
b)
c)
d)
e)
f)
g)
MOV
MOV
MOV
MOV
TBLWTL
MOV
MOV
DISI
MOV
MOV
MOV
MOV
BSET
NOP
NOP
Writing to the Data EEPROM
Select word, data EEPROM erase, and set
WREN bit in NVMCON register.
Write address of word to be erased into
NVMADR.
Enable NVM interrupt (optional).
Write ‘0x55’ to NVMKEY.
Write ‘0xAA’ to NVMKEY.
Set the WR bit. This begins erase cycle.
Either poll NVMIF bit or wait for NVMIF
interrupt.
The WR bit is cleared when the erase cycle
ends.
Select word, data EEPROM program, and
set WREN bit in NVMCON register.
Enable NVM write done interrupt (optional).
Write ‘0x55’ to NVMKEY.
Write ‘0xAA’ to NVMKEY.
Set the WR bit. This begins program cycle.
Either poll NVMIF bit or wait for NVM
interrupt.
The WR bit is cleared when the write cycle
ends.
#LOW_ADDR_WORD,W0
#HIGH_ADDR_WORD,W1
W1
#LOW(WORD),W2
W2
#0x4004,W0
W0
#5
#0x55,W0
W0
#0xAA,W1
W1
NVMCON,#WR
,
,
,
,
,
DATA EEPROM WORD WRITE
TBLPAG
[ W0]
NVMCON
NVMKEY
NVMKEY
dsPIC30F2011/2012/3012/3013
; Init pointer
; Get data
; Initiate program sequence
; Write data
; Block all interrupts with priority <7 for
; next 5 instructions
; Write the 0x55 key
; Write the 0xAA key
The write does not initiate if the above sequence is not
exactly followed (write 0x55 to NVMKEY, write 0xAA to
NVMCON, then set WR bit) for each word. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in NVMCON must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code
execution. The WREN bit should be kept clear at all
times except when updating the EEPROM. The WREN
bit is not cleared by hardware.
After a write sequence has been initiated, clearing the
WREN bit does not affect the current write cycle. The
WR bit is inhibited from being set unless the WREN bit
is set. The WREN bit must be set on a previous
instruction. Both WR and WREN cannot be set with the
same instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the Nonvolatile Memory Write
Complete Interrupt Flag bit (NVMIF) is set. The user
may either enable this interrupt or poll this bit. NVMIF
must be cleared by software.
6.3.1
Once the user has erased the word to be programmed,
then a table write instruction is used to write one write
latch, as shown in Example 6-4.
6.3.2
To write a block of data EEPROM, write to all sixteen
latches first, then set the NVMCON register and
program the block.
WRITING A WORD OF DATA
EEPROM
WRITING A BLOCK OF DATA
EEPROM
DS70139F-page 57