DSPIC30F2011-20I/ML Microchip Technology, DSPIC30F2011-20I/ML Datasheet - Page 109
DSPIC30F2011-20I/ML
Manufacturer Part Number
DSPIC30F2011-20I/ML
Description
IC DSPIC MCU/DSP 12K 28QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20ISO.pdf
(210 pages)
3.DSPIC30F2011-20ISO.pdf
(14 pages)
4.DSPIC30F2011-20ISO.pdf
(6 pages)
5.DSPIC30F2011-20ISO.pdf
(18 pages)
6.DSPIC30F2011-20IP.pdf
(206 pages)
Specifications of DSPIC30F2011-20I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
12
Flash Memory Size
12KB
Supply Voltage Range
2.5V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DAF30-4 - DEVICE ATP FOR ICE4000
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F201120IML
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F2011-20I/ML
Manufacturer:
Microchip Technology
Quantity:
135
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F2011-20ISO PDF datasheet #2
- DSPIC30F2011-20ISO PDF datasheet #3
- DSPIC30F2011-20ISO PDF datasheet #4
- DSPIC30F2011-20ISO PDF datasheet #5
- DSPIC30F2011-20IP PDF datasheet #6
- Current page: 109 of 206
- Download datasheet (3Mb)
TABLE 15-1:
TABLE 15-2:
SFR Name Addr.
U1MODE
U1STA
U1TXREG
U1RXREG
U1BRG
Legend:
U2MODE
U2STA
U2TXREG
U2RXREG
U2BRG
Legend:
Note
Name
SFR
1:
2:
020C
020E
Addr.
021C
0210
0212
0214
0216
0218
021A
021E
u = uninitialized bit; — = unimplemented bit, read as ‘0’
u = uninitialized bit; — = unimplemented bit, read as ‘0’
UART2 is not available on dsPIC30F2011/2012/3012 devices.
Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
UARTEN
UTXISEL
UARTEN
UTXISEL
UART1 REGISTER MAP FOR dsPIC30F2011/2012/3012/3013
UART2 REGISTER MAP FOR dsPIC30F3013
Bit 15
Bit 15
—
—
—
—
Bit 14
Bit 14
—
—
—
—
—
—
—
—
USIDL
Bit 13
USIDL
Bit 13
—
—
—
—
—
—
Bit 12
Bit 12
—
—
—
—
—
—
—
—
UTXBRK UTXEN UTXBF
UTXBRK UTXEN
Bit 11
Bit 11
—
—
—
—
—
—
Bit 10
Bit 10
ALTIO
—
—
—
—
—
Bit 9
UTXBF
—
—
—
Bit 9
—
—
—
Baud Rate Generator Prescaler
Baud Rate Generator Prescaler
(1)
TRMT
URX8
UTX8
Bit 8
TRMT
—
UTX8
URX8
Bit 8
—
URXISEL1 URXISEL0 ADDEN
URXISEL1 URXISEL0 ADDEN RIDLE
WAKE
Bit 7
WAKE
Bit 7
LPBACK
LPBACK
Bit 6
Bit 6
ABAUD
Bit 5
ABAUD
Bit 5
Transmit Register
Receive Register
Transmit Register
Receive Register
RIDLE
Bit 4
Bit 4
—
—
PERR
PERR
Bit 3
Bit 3
—
—
PDSEL1 PDSEL0
PDSEL1 PDSEL0 STSEL 0000 0000 0000 0000
FERR
Bit 2
FERR
Bit 2
OERR
OERR
Bit 1
Bit 1
URXDA 0000 0001 0001 0000
URXDA 0000 0001 0001 0000
STSEL 0000 0000 0000 0000
Bit 0
Bit 0
0000 000u uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
0000 000u uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
Reset State
Reset State
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