PIC18LF1320-I/P Microchip Technology, PIC18LF1320-I/P Datasheet - Page 227
![IC MCU FLASH 4KX16 EEPROM 18DIP](/photos/6/76/67657/18-dip_300mil__sml.jpg)
PIC18LF1320-I/P
Manufacturer Part Number
PIC18LF1320-I/P
Description
IC MCU FLASH 4KX16 EEPROM 18DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F1220-ISO.pdf
(308 pages)
3.PIC18F1220-ISO.pdf
(8 pages)
4.PIC18F1220-ISO.pdf
(6 pages)
5.PIC18F1220-ISO.pdf
(10 pages)
6.PIC18F1220-ISO.pdf
(4 pages)
Specifications of PIC18LF1320-I/P
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
16
Eeprom Memory Size
256Byte
Ram Memory Size
256Byte
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
16
Number Of Timers
1 x 16 bit
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
7
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF1320-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F1220-ISO PDF datasheet #2
- PIC18F1220-ISO PDF datasheet #3
- PIC18F1220-ISO PDF datasheet #4
- PIC18F1220-ISO PDF datasheet #5
- PIC18F1220-ISO PDF datasheet #6
- Current page: 227 of 308
- Download datasheet (5Mb)
RRNCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example 1:
Example 2:
© 2007 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
REG
REG
W
REG
W
REG
Q1
=
=
=
=
=
=
register ‘f’
Rotate Right f (no carry)
[ label ]
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f<n>) → dest<n – 1>,
(f<0>) → dest<7>
N, Z
The contents of register ‘f’ are
rotated one bit to the right. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is
‘1’, the result is placed back in
register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ is
‘1’, then the bank will be selected
as per the BSR value (default).
1
1
RRNCF
RRNCF
Read
0100
Q2
1101 0111
1110 1011
?
1101 0111
1110 1011
1101 0111
REG, 1, 0
REG, W
RRNCF
00da
Process
Data
Q3
register f
ffff
f [,d [,a]]
destination
Write to
Q4
ffff
SETF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
REG
PIC18F1220/1320
Q1
register ‘f’
Set f
[ label ] SETF
0 ≤ f ≤ 255
a ∈ [0,1]
FFh → f
None
The contents of the specified
register are set to FFh. If ‘a’ is ‘0’,
the Access Bank will be selected,
overriding the BSR value. If ‘a’ is
‘1’, then the bank will be selected
as per the BSR value (default).
1
1
SETF
Read
0110
Q2
=
=
0x5A
0xFF
REG
100a
Process
Data
Q3
f [,a]
DS39605F-page 225
ffff
register ‘f’
Write
Q4
ffff
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