PIC16F636-I/P Microchip Technology, PIC16F636-I/P Datasheet - Page 77
![IC MCU FLASH 2KX14 14DIP](/photos/6/59/65935/150-14-dip_sml.jpg)
PIC16F636-I/P
Manufacturer Part Number
PIC16F636-I/P
Description
IC MCU FLASH 2KX14 14DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC12F635-ISN.pdf
(234 pages)
3.PIC16F636-ISL.pdf
(8 pages)
4.PIC16F636-ISL.pdf
(4 pages)
5.PIC16F636-IST.pdf
(196 pages)
Specifications of PIC16F636-I/P
Program Memory Type
FLASH
Program Memory Size
3.5KB (2K x 14)
Package / Case
14-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, LVD, POR, WDT
Number Of I /o
11
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
RS- 232/SPI/USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164039 - MODULE SKT PROMATE II 20DIP/SOICAC162057 - MPLAB ICD 2 HEADER 14DIPACICE0207 - MPLABICE 14P 300 MIL ADAPTER
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
9.2
To read a data memory location, the user must write the
address to the EEADR register and then set control bit
RD (EECON1<0>), as shown in Example 9-1. The data
is available, in the very next cycle, in the EEDAT
register. Therefore, it can be read in the next
instruction. EEDAT holds this value until another read,
or until it is written to by the user (during a write
operation).
EXAMPLE 9-1:
9.3
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDAT register. Then the user must follow a
specific sequence to initiate the write for each byte, as
shown in Example 9-2.
EXAMPLE 9-2:
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment. A cycle count is executed during the
required sequence. Any number that is not equal to the
required cycles to execute the required sequence will
prevent the data from being written into the EEPROM.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
© 2005 Microchip Technology Inc.
BSF
BCF
MOVLW
MOVWF
BSF
MOVF
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
Reading the EEPROM Data
Memory
Writing to the EEPROM Data
Memory
STATUS,RP0
STATUS,RP1
CONFIG_ADDR
EEADR
EECON1,RD
EEDAT,W
STATUS,RP0
STATUS,RP1
EECON1,WREN
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON1,WR
INTCON,GIE
DATA EEPROM READ
DATA EEPROM WRITE
;Bank 1
;
;
;Address to read
;EE Read
;Move data to W
;Bank 1
;
;Enable write
;Disable INTs
;Unlock write
;
;
;
;Start the write
;Enable INTS
PIC12F635/PIC16F636/639
Preliminary
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. The EEIF bit
(PIR1<7>) must be cleared by software.
9.4
Depending on the application, good programming
practice may dictate that the value written to the data
EEPROM should be verified (see Example 9-3) to the
desired value to be written.
EXAMPLE 9-3:
9.4.1
The data EEPROM is a high-endurance, byte
addressable array that has been optimized for the
storage of frequently changing information (e.g.,
program variables or other data that are updated often).
The maximum endurance for any EEPROM cell is
specified as D120. D124 specifies a maximum number
of writes to any EEPROM location before a refresh is
required of infrequently changing memory locations.
9.4.2
As an example, hypothetically, a data EEPROM is
64 bytes long and has an endurance of 1M writes. It
also has a refresh parameter of 10M writes. If every
memory location in the cell were written the maximum
number of times, the data EEPROM would fail after
64M write cycles. If every memory location, save 1,
were written the maximum number of times, the data
EEPROM would fail after 63M write cycles, but the one
remaining location could fail after 10M cycles. If proper
refreshes occurred, then the lone memory location
would have to be refreshed 6 times for the data to
remain correct.
BSF
BCF
MOVF
BSF
XORWF
BTFSS
GOTO
:
Write Verify
USING THE DATA EEPROM
EEPROM ENDURANCE
STATUS,RP0
STATUS,RP1
EEDAT,W
EECON1,RD
EEDAT,W
STATUS,Z
WRITE_ERR
WRITE VERIFY
;Bank 1
;
;EEDAT not changed
;from previous write
;YES, Read the
;value written
;Is data the same
;No, handle error
;Yes, continue
DS41232B-page 75