SAK-TC1762-128F80HL AC Infineon Technologies, SAK-TC1762-128F80HL AC Datasheet - Page 98

• Manufacturer Part Number: SAK-TC1762-128F80HL AC
• Description: IC MCU 32BIT FLASH PG-LQFP-176
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1762-128F80HL AC

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 81
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 2x10b; A/D 32x8b,10b,12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 176-LFQFP
• Packages: PG-LQFP-176
• Max Clock Frequency: 80.0 MHz
• Sram (incl. Cache): 52.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 1.0 MB
• For Use With: B158-H8539-G2-X-7600IN - KIT STARTER TC176X SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: KT1762128F80HLACXT; SAK-TC1762-128F80HLACINTR; SP000318061

Preliminary
2) This parameter is verified by device characterization. The external oscillator circuitry must be optimized by the
3) Any HDRST activation is internally prolonged to 1024 FPI bus clock (
4) Applicable for input pins TESTMODE, TRST, BRKIN, and TXD1A with noise suppression filter of PORST
5) The setup/hold values are applicable for Port 0 and Port 4 input pins with noise suppression filter of HDRST
6) Not subject to production test, verified by design / characterization.
7) This parameter includes the delay of the analog spike filter in the PORST pad.
8) Not subject to production test, verified by design / characterization.
9) In case of power loss during internal flash write, prevents Flash write to random address.
10) Booting from Flash, the duration of the boot-time is defined between the rising edge of the PORST and the
11) Booting from Flash, the duration of the boot time is defined between the following events:
Figure 4-11 Power, Pad and Reset Timing
Data Sheet
PORST
Pads
HDRST
VDDP
OSC
VDD
customer and checked for negative resistance as recommended and specified by crystal suppliers.
switched-on (BYPASS = 0).
switched-on (BYPASS = 0), independently whether HDRST is used as input or output.
moment when the first user instruction has entered the CPU and its processing starts.
1. Hardware reset: the falling edge of a short HDRST pulse and the moment when the first user instruction has
entered the CPU and its processing starts, if the HDRST pulse is shorter than 1024 ×
If the HDRST pulse is longer than 1024 ×
boot time (HDRST falling edge to first user instruction).
2. Software reset: the moment of starting the software reset and the moment when the first user instruction
has entered the CPU and its processing starts
V
DDPPA
undefined
state
Pad-
t
oscs
t
POA
t
POA
2)
t
1) as programmed
hd
2) Tri-state, pull device active
T
SYS
, only the time beyond the 1024 ×
1)
94
t
pi
t
hd
2)
f
SYS
) cycles.
1)
Electrical Parameters
T
SYS
should be added to the
T
reset_beh
SYS
V
DDPR
2)
.
undefined
V1.0, 2008-04
state
Pad-
V
TC1762
DDPPA