SAK-TC1762-128F80HL AC Infineon Technologies, SAK-TC1762-128F80HL AC Datasheet - Page 39

• Manufacturer Part Number: SAK-TC1762-128F80HL AC
• Description: IC MCU 32BIT FLASH PG-LQFP-176
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1762-128F80HL AC

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 81
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 52K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 2x10b; A/D 32x8b,10b,12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 176-LFQFP
• Packages: PG-LQFP-176
• Max Clock Frequency: 80.0 MHz
• Sram (incl. Cache): 52.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 1.0 MB
• For Use With: B158-H8539-G2-X-7600IN - KIT STARTER TC176X SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: KT1762128F80HLACXT; SAK-TC1762-128F80HLACINTR; SP000318061

Preliminary
3.8
Figure 3-4
Synchronous Serial Interface, SSC0.
Figure 3-4
The SSC supports full-duplex and half-duplex serial synchronous communication up to
40.0 MBaud at 80 MHz module clock and up to 33 MBaud at 66 MHz module clock. The
serial clock signal can be generated by the SSC itself (Master Mode) or can be received
from an external master (Slave Mode). Data width, shift direction, clock polarity and
phase are programmable. This allows communication with SPI-compatible devices.
Transmission and reception of data is double-buffered. A shift clock generator provides
the SSC with a separate serial clock signal. Seven slave select inputs are available for
Data Sheet
To
DMA
Address
Decoder
Interrupt
Control
Control
Clock
SSC0_RDR
SSC0_TDR
M/S Select
shows a global view of the functional blocks and interfaces of the high-speed
High-Speed Synchronous Serial Interface (SSC0)
Enable
Block Diagram of the SSC Interfaces
EIR
TIR
RIR
f
f
SSC 0
C L C0
1 )
1 )
1) These lines are not connected
(Kernel)
Module
SSC0
Master
Master
Master
Slave
Slave
Slave
35
SLSI1
SLSI[7:2]
SLSO[2:0]
MRSTA
MRSTB
MTSR
MTSRA
MTSRB
MRST
SCLKA
SCLKB
SCLK
SLSO[5:3]
SLSO6
SLSO7
1)
1 )
Control
Control
Port 3
Port 2
Functional Description
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
P3.4 /MTSR0
P3.3 /MRST0
P3.2 /SCLK0
P3.7 /SLSI0
P2.1 /SLSO03
P2.8 /SLSO04
P2.9 /SLSO05
P3.5 /SLSO00
P3.6 /SLSO01
P3.7 /SLSO02
P3.8 /SLSO06
V1.0, 2008-04
MCB06225
TC1762