SAK-C164CI-8EM CB Infineon Technologies, SAK-C164CI-8EM CB Datasheet - Page 54
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SAK-C164CI-8EM CB
Manufacturer Part Number
SAK-C164CI-8EM CB
Description
IC MCU 16BIT 64KB OTP MQFP-80-1
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet
1.SAF-C164CI-8EM_CB.pdf
(79 pages)
Specifications of SAK-C164CI-8EM CB
Core Processor
C166
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, EBI/EMI, SPI, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
59
Program Memory Size
64KB (64K x 8)
Program Memory Type
OTP
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.75 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
80-SQFP
Packages
PG-MQFP-80
Max Clock Frequency
20.0 MHz
Sram (incl. Cache)
4.0 KByte
Can Nodes
1
A / D Input Lines (incl. Fadc)
8
Program Memory
64.0 KByte
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
K164CI8EMCBNP
K164CI8EMCBXP
SAK-C164CI-8EMCB
SAK-C164CI-8EMCB
SAK-C164CI-8EMCBIN
SAKC164CI8EMCBX
SP000103500
K164CI8EMCBXP
SAK-C164CI-8EMCB
SAK-C164CI-8EMCB
SAK-C164CI-8EMCBIN
SAKC164CI8EMCBX
SP000103500
AC Characteristics
Definition of Internal Timing
The internal operation of the C164CI is controlled by the internal CPU clock
edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)
operations.
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called “TCL” (see
Figure 11
The CPU clock signal
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate
be regarded when calculating the timings for the C164CI.
Note: The example for PLL operation shown in
The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG
in register RP0H.7-5.
Upon a long hardware reset register RP0H is loaded with the logic levels present on the
upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins
Data Sheet
Phase Locked Loop Operation
f
f
Direct Clock Drive
f
f
Prescaler Operation
f
f
OSC
CPU
OSC
CPU
OSC
CPU
Generation Mechanisms for the CPU Clock
f
CPU
can be generated from the oscillator clock signal
50
Figure 11
refers to a PLL factor of 4.
TCL
f
CPU
TCL
. This influence must
TCL
TCL
TCL
TCL
MCT04338
Figure
C164CL/SL
V2.0, 2001-05
C164CI/SI
f
CPU
f
OSC
. Both
11).
via