SAK-C164CI-8EM CB Infineon Technologies, SAK-C164CI-8EM CB Datasheet - Page 33
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SAK-C164CI-8EM CB
Manufacturer Part Number
SAK-C164CI-8EM CB
Description
IC MCU 16BIT 64KB OTP MQFP-80-1
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet
1.SAF-C164CI-8EM_CB.pdf
(79 pages)
Specifications of SAK-C164CI-8EM CB
Core Processor
C166
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, EBI/EMI, SPI, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
59
Program Memory Size
64KB (64K x 8)
Program Memory Type
OTP
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.75 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
80-SQFP
Packages
PG-MQFP-80
Max Clock Frequency
20.0 MHz
Sram (incl. Cache)
4.0 KByte
Can Nodes
1
A / D Input Lines (incl. Fadc)
8
Program Memory
64.0 KByte
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
K164CI8EMCBNP
K164CI8EMCBXP
SAK-C164CI-8EMCB
SAK-C164CI-8EMCB
SAK-C164CI-8EMCBIN
SAKC164CI8EMCBX
SP000103500
K164CI8EMCBXP
SAK-C164CI-8EMCB
SAK-C164CI-8EMCB
SAK-C164CI-8EMCBIN
SAKC164CI8EMCBX
SP000103500
Oscillator Watchdog
The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip
oscillator (either with a crystal or via external clock drive). For this operation the PLL
provides a clock signal which is used to supervise transitions on the oscillator clock. This
PLL clock is independent from the XTAL1 clock. When the expected oscillator clock
transitions are missing the OWD activates the PLL Unlock/OWD interrupt node and
supplies the CPU with the PLL clock signal. Under these circumstances the PLL will
oscillate with its basic frequency.
In direct drive mode the PLL base frequency is used directly (
In prescaler mode the PLL base frequency is divided by 2 (
Note: The CPU clock source is only switched back to the oscillator clock after a
The oscillator watchdog can be disabled by setting bit OWDDIS in register SYSCON.
In this case (OWDDIS = ‘1’) the PLL remains idle and provides no clock signal, while the
CPU clock signal is derived directly from the oscillator clock or via prescaler or SDD. Also
no interrupt request will be generated in case of a missing oscillator clock.
Note: At the end of a reset bit OWDDIS reflects the inverted level of pin RD at that time.
Data Sheet
hardware reset.
Thus the oscillator watchdog may also be disabled via hardware by (externally)
pulling the RD line low upon a reset, similar to the standard reset configuration via
PORT0.
29
f
CPU
f
CPU
= 1 … 2.5 MHz).
= 2 … 5 MHz).
C164CL/SL
V2.0, 2001-05
C164CI/SI