SAF-XE167F-48F66L AC Infineon Technologies, SAF-XE167F-48F66L AC Datasheet - Page 117

IC MCU 16BIT FLASH PG-LQFP-144

SAF-XE167F-48F66L AC

Manufacturer Part Number
SAF-XE167F-48F66L AC
Description
IC MCU 16BIT FLASH PG-LQFP-144
Manufacturer
Infineon Technologies
Series
XE16xr
Datasheet

Specifications of SAF-XE167F-48F66L AC

Core Processor
C166SV2
Core Size
16-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
Peripherals
I²S, POR, PWM, WDT
Number Of I /o
118
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
34K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
FXE167F48F66LACXP
SAF-XE167F-48F66LACIN
SP000363821
SP000363822
4.6.6
The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: These parameters are not subject to production test but verified by design and/or
Table 35
Parameter
TCK clock period
TCK high time
TCK low time
TCK clock rise time
TCK clock fall time
TDI/TMS setup
to TCK rising edge
TDI/TMS hold
after TCK rising edge
TDO valid
after TCK falling edge
TDO high imped. to valid
from TCK falling edge
TDO valid to high imped.
from TCK falling edge
1) The falling edge on TCK is used to generate the TDO timing.
2) The setup time for TDO is given implicitly by the TCK cycle time.
Data Sheet
characterization.
JTAG Interface Timing
JTAG Interface Timing Parameters
(Operating Conditions apply)
1)
1)2)
1)
Symbol
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
8
9
10
SR
SR
SR
SR
SR
SR
SR
CC
CC
CC
CC
Min.
60
16
16
6
6
10
115
Values
Typ.
50
30
30
30
Max.
8
8
XE166 Family Derivatives
Unit Note /
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Electrical Parameters
Test Condition
C
C
C
C
L
L
L
L
= 50 pF
= 20 pF
= 50 pF
= 50 pF
V2.1, 2008-08
XE167x

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