SAF-C161PI-LF 3V CA Infineon Technologies, SAF-C161PI-LF 3V CA Datasheet - Page 60
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SAF-C161PI-LF 3V CA
Manufacturer Part Number
SAF-C161PI-LF 3V CA
Description
IC MCU 16BIT ROM/LESS TQFP-100-1
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet
1.SAF-C161PI-LM_CA.pdf
(82 pages)
Specifications of SAF-C161PI-LF 3V CA
Core Processor
C166
Core Size
16-Bit
Speed
20MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
76
Program Memory Type
ROMless
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFQFP
Data Bus Width
16 bit
Data Ram Size
3 KB
Interface Type
ASC, I2C, SSC
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
76
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Packages
PG-TQFP-100
Max Clock Frequency
20.0 MHz
Sram (incl. Cache)
3.0 KByte
A / D Input Lines (incl. Fadc)
4
Program Memory
0.0 KByte
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
F161PILF3VCAXT
SAF-C161PI-LF3VCA
SAF-C161PI-LF3VCAINTR
SAF-C161PI-LF3VCATR
SAF-C161PI-LF3VCATR
SAFC161PILF3VCAXT
SP000014361
SAF-C161PI-LF3VCA
SAF-C161PI-LF3VCAINTR
SAF-C161PI-LF3VCATR
SAF-C161PI-LF3VCATR
SAFC161PILF3VCAXT
SP000014361
Data Sheet
Multiplexed Bus (Reduced Supply Voltage Range) (continued)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2
Parameter
Data valid to WR
Data hold after WR
ALE rising edge after RD,
WR
Address hold after RD,
WR
ALE falling edge to CS
CS low to Valid Data In
CS hold after RD, WR
ALE fall. edge to RdCS,
WrCS (with RW delay)
ALE fall. edge to RdCS,
WrCS (no RW delay)
Address float after RdCS,
WrCS (with RW delay)
Address float after RdCS,
WrCS (no RW delay)
RdCS to Valid Data In
(with RW delay)
RdCS to Valid Data In
(no RW delay)
RdCS, WrCS Low Time
(with RW delay)
RdCS, WrCS Low Time
(no RW delay)
Data valid to WrCS
1)
1)
1)
Symbol
22
23
25
27
38
39
40
42
43
44
45
46
47
48
49
50
A
+
CC 24 +
CC 36 +
CC 36 +
CC 36 +
CC -8 -
CC 57 +
CC 19 +
CC -6 +
CC –
CC –
CC 38 +
CC 63 +
CC 28 +
SR –
SR –
SR –
C
+
F
Max. CPU Clock
(150 ns at 20 MHz CPU clock without waitstates)
min.
= 20 MHz
A
A
58
C
F
F
F
F
A
C
C
C
–
–
–
–
10 -
47
+
–
–
–
0
25
20 +
45 +
–
–
–
max.
C
+ 2
A
C
C
A
1 / 2TCL = 1 to 20 MHz
2TCL - 26
+
2TCL - 14
+
2TCL - 14
+
2TCL - 14
+
-8 -
–
3TCL - 18
+
TCL - 6
+
-6
+
–
–
–
–
2TCL - 12
+
3TCL - 12
+
2TCL - 22
+
Variable CPU Clock
C
F
F
F
A
A
C
C
C
F
min.
A
–
–
–
–
10 -
3TCL - 28
+
–
–
–
0
TCL
2TCL - 30
+
3TCL - 30
+
–
–
–
C
C
C
max.
+ 2
A
A
&3,
1999-07
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns