ADUC7128BSTZ126-RL Analog Devices Inc, ADUC7128BSTZ126-RL Datasheet - Page 71

• Manufacturer Part Number: ADUC7128BSTZ126-RL
• Description: IC DAS MCU ARM7 ADC/DDS 64-LQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7128BSTZ126-RL

• Core Size: 16/32-Bit
• Program Memory Size: 126KB (126K x 8)
• Core Processor: ARM7
• Speed: 41.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: PLA, POR, PWM, PSM, Temp Sensor, WDT
• Number Of I /o: 28
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x12b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Controller Family/series: (ARM7) ADUC
• No. Of I/o's: 40
• Cpu Speed: 41.78MHz
• No. Of Timers: 5
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADUC7128QSPZ - KIT DEV FOR ADUC7128
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: ADUC7128BSTZ126-RLTR

Table 99. PLACLK MMR Bit Designations
Bit
7
6:4
3
2:0
Table 100. PLAIRQ MMR Bit Designations
Bit
15:13
12
11:8
7:5
4
3:0
Value
0000
0001
…
1111
0000
0001
…
1111
Value
000
001
010
011
100
101
110
Other
000
001
010
011
100
101
110
Other
Description
Reserved.
Block 1 Clock Source Selection.
GPIO Clock on P0.5.
GPIO Clock on P0.0.
GPIO Clock on P0.7.
HCLK.
OCLK.
Timer1 Overflow.
Timer4 Overflow.
Reserved.
Reserved.
Block 0 Clock Source Selection.
GPIO Clock on P0.5.
GPIO Clock on P0.0.
GPIO Clock on P0.7.
HCLK.
OCLK.
Timer1 Overflow.
Timer4 Overflow.
Reserved.
Description
Reserved.
PLA IRQ1 Enable Bit
PLA IRQ1 Source.
PLA Element 0.
PLA Element 1.
PLA Element 15.
Reserved.
PLA IRQ0 Enable Bit.
PLA IRQ0 Source.
PLA Element 0.
PLA Element 1.
PLA Element 15.
Set by user to enable IRQ1 output from PLA
Cleared by user to disable IRQ1 output
from PLA
Set by user to enable IRQ0 output from PLA.
Cleared by user to disable IRQ0 output
from PLA.
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Table 101. PLAADC MMR Bit Designations
Bit
31:5
4
3:0
Table 102. PLADIN MMR Bit Designations
Bit
31:16
15:0
Table 103. PLAOUT MMR Bit Designations
Bit
31:16
15:0
Value
0000
0001
…
1111
Description
Reserved.
Input Bit from Element 15 to Element 0.
Description
Reserved.
Output Bit from Element 15 to Element 0.
Description
Reserved.
ADC Start Conversion Enable Bit.
ADC Start Conversion Source.
PLA Element 0.
PLA Element 1.
PLA Element 15.
conversion from PLA.
Set by user to enable ADC start conversion
from PLA.
Cleared by user to disable ADC start