HD64F7145F50V Renesas Electronics America, HD64F7145F50V Datasheet - Page 603
![IC SUPERH MCU FLASH 256K 144QFP](/photos/12/22/122200/hd64f7145f50v_sml.jpg)
HD64F7145F50V
Manufacturer Part Number
HD64F7145F50V
Description
IC SUPERH MCU FLASH 256K 144QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Specifications of HD64F7145F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F7145F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F7145F50V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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15.7.4
If the conditions below are not met, the reliability of the device may be adversely affected.
• Analog input voltage range
• Relationship between AVcc, Avss and Vcc, Vss
• Setting range of AVref input voltage (only for SH7145)
15.7.5
In board design, digital circuitry and analog circuitry should be as mutually isolated as possible,
and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close
proximity should be avoided as far as possible. Failure to do so may result in incorrect operation
of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital
circuitry must be isolated from the analog input signals (AN0 to AN7), and analog power supply
(AVcc) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one
point to a stable digital ground (Vss) on the board.
15.7.6
A protection circuit should be connected in order to prevent damage due to abnormal voltage, such
as an excessive surge at the analog input pins (AN0 to AN7), to AVcc and AVss, as shown in
figure 15.7. Also, the bypass capacitors connected to AVcc and the filter capacitor connected to
AN0 to AN7 must be connected to AVss.
If a filter capacitor is connected, the input currents at the analog input pins (AN0 to AN7) are
averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in
scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit
in the A/D converter exceeds the current input via the input impedance (R
the analog input pin voltage. Careful consideration is therefore required when deciding circuit
constants.
The voltage applied to analog input pin ANn (VANn) during A/D conversion should be in the
range AVss ≤ VANn ≤ AVcc.
The Relationship between AVcc, AVss and Vcc, Vss should be AVcc = Vcc ± 0.3V and Avss
= Vss. If the A/D converter is not used, this relationship should be AVcc = Vcc and Avss =
Vss.
Set the AVref pin input voltage as AVref ≤ AVcc. If the A/D converter is not used, set the
AVref pin as AVref = AVcc.
Range of Analog Power Supply and Other Pin Settings
Notes on Board Design
Notes on Noise Countermeasures
Rev.4.00 Mar. 27, 2008 Page 557 of 882
in
), an error will arise in
15. A/D Converter
REJ09B0108-0400
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