HD64F7145F50V Renesas Electronics America, HD64F7145F50V Datasheet - Page 223
![IC SUPERH MCU FLASH 256K 144QFP](/photos/12/22/122200/hd64f7145f50v_sml.jpg)
HD64F7145F50V
Manufacturer Part Number
HD64F7145F50V
Description
IC SUPERH MCU FLASH 256K 144QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Specifications of HD64F7145F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F7145F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F7145F50V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Bit
1
0
Notes: 1. TE bit: Allows only 0 write after reading 1.
Bit Name
TE
DE
2. The DI, RO, RL, AM, AL, or DS bit may be absent, depending on the channel.
Initial Value
0
0
R/W
R/(W)*
R/W
1
Description
Transfer End Flag
This bit is set to 1 after the number of data transfers
specified by the DMATCR. At this time, if the IE bit is
set to 1, an interrupt request is generated.
If data transfer ends before TE is set to 1 (for
example, due to an NMI or address error, or clearing
of the DE bit or DME bit of the DMAOR) the TE is not
set to 1. With this bit set to 1, data transfer is disabled
even if the DE bit is set to 1.
0: DMATCR-specified transfer count not ended
[Clearing condition]
0 write after TE = 1 read, power-on reset, software
standby mode
1: DMATCR specified number of transfers
DMAC Enable
DE enables operation in the corresponding channel.
0: Operation of the corresponding channel disabled
1: Operation of the corresponding channel enabled
Transfer mode is entered if this bit is set to 1 when
auto-request is specified (RS3 to RS0 settings). With
an external request or on-chip module request, when
a transfer request occurs after this bit is set to 1,
transfer is enabled. If this bit is cleared during a data
transfer, transfer is suspended.
If the DE bit has been set, but TE = 1, then if the
DME bit of the DMAOR is 0, and the NMI or AE bit of
the DMAOR is 1, transfer enable mode is not entered.
completed
10. Direct Memory Access Controller (DMAC)
Rev.4.00 Mar. 27, 2008 Page 177 of 882
REJ09B0108-0400
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