MC9S12C128MFAE Freescale Semiconductor, MC9S12C128MFAE Datasheet - Page 80
![IC MCU 128K FLASH 25MHZ 48-LQFP](/photos/12/20/122066/mc9s12c128mfae_sml.jpg)
MC9S12C128MFAE
Manufacturer Part Number
MC9S12C128MFAE
Description
IC MCU 128K FLASH 25MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12C128MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
48LQFP
Family Name
HCS12
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12C128MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 2 Port Integration Module (PIM9C32) Block Description
2.3.2
Table 2-2
level (I/O), reduced drive (RDR), pull enable (PE), pull select (PS), and interrupt enable (IE) for the ports.
The configuration bit PS is used for two purposes:
1. Applicable only on ports P and J.
80
DDR
1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled.
2. Select either a pull-up or pull-down device if PE is active.
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
summarizes the effect on the various configuration bits — data direction (DDR), input/output
IO
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
Register Descriptions
All bits of all registers in this module are completely synchronous to internal
clocks during a register read.
RDR
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
PE
X
X
X
X
X
X
X
X
0
1
1
0
0
1
1
PS
X
0
1
0
1
0
1
X
X
X
X
0
1
0
1
Table 2-2. Pin Configuration Summary
MC9S12C-Family / MC9S12GC-Family
IE
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
(1)
Output, reduced drive to 0
Output, reduced drive to 1
Output, reduced drive to 0
Output, reduced drive to 1
Rev 01.24
Output, full drive to 0
Output, full drive to 1
Output, full drive to 0
Output, full drive to 1
NOTE
Function
Input
Input
Input
Input
Input
Input
Input
Pull Device
Pull down
Pull down
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Pull up
Pull up
Freescale Semiconductor
Falling edge
Rising edge
Falling edge
Falling edge
Rising edge
Falling edge
Rising edge
rising edge
Interrupt
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
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