MC9S12C128MFAE Freescale Semiconductor, MC9S12C128MFAE Datasheet - Page 272
![IC MCU 128K FLASH 25MHZ 48-LQFP](/photos/12/20/122066/mc9s12c128mfae_sml.jpg)
MC9S12C128MFAE
Manufacturer Part Number
MC9S12C128MFAE
Description
IC MCU 128K FLASH 25MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12C128MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
48LQFP
Family Name
HCS12
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12C128MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
9.4.5
The COP (free running watchdog timer) enables the user to check that a program is running and
sequencing properly. The COP is disabled out of reset. When the COP is being used, software is
responsible for keeping the COP from timing out. If the COP times out it is an indication that the software
is no longer being executed in the intended sequence; thus a system reset is initiated (see
“Computer Operating Properly Watchdog (COP)
Section Figure 9-21., “Clock Chain for
of seven COP time-out periods.
When COP is enabled, the program must write 0x0055 and 0x00AA (in this order) to the ARMCOP
register during the selected time-out period. As soon as this is done, the COP time-out period is restarted.
If the program fails to do this and the COP times out, the part will reset. Also, if any value other than
0x0055 or 0x00AA is written, the part is immediately reset.
Windowed COP operation is enabled by setting WCOP in the COPCTL register. In this mode, writes to
the ARMCOP register to clear the COP timer must occur in the last 25% of the selected time-out period.
A premature write will immediately reset the part.
If PCE bit is set, the COP will continue to run in pseudo-stop mode.
9.4.6
The RTI can be used to generate a hardware interrupt at a fixed periodic rate. If enabled (by setting
RTIE=1), this interrupt will occur at the rate selected by the RTICTL register. The RTI runs with a gated
OSCCLK (see
RTIF flag is set to 1 and a new RTI time-out period starts immediately.
A write to the RTICTL register restarts the RTI time-out period.
272
Computer Operating Properly Watchdog (COP)
Real-Time Interrupt (RTI)
OSCCLK
Section Figure 9-22., “Clock Chain for
gating condition
= Clock Gate
STOP(PSTP,PCE),
WAIT(COPWAI),
COP enable
Figure 9-21. Clock Chain for COP
MC9S12C-Family / MC9S12GC-Family
COP”). Three control bits in the COPCTL register allow selection
CR[2:0]
0:0:0
Rev 01.24
Reset).” The COP runs with a gated OSCCLK (see
÷
16384
RTI”). At the end of the RTI time-out period the
÷
÷
÷
÷
÷
÷
4
4
2
2
4
4
CR[2:0]
0:1:0
0:1:1
1:1:0
0:0:1
1:0:0
1:0:1
1:1:1
COP TIMEOUT
Freescale Semiconductor
Section 9.5.2,
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