M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 220

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

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14.1.3.7 ACK and NACK
14.1.3.8 Initialization of Transmission/Reception
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If the STSPSEL bit in the U2SMR4 register is set to “0” (start and stop conditions not generated) and
the ACKC bit in the U2SMR4 register is set to “1” (ACK data output), the value of the ACKD bit in the
U2SMR4 register is output from the SDA
If the IICM2 bit is set to "0", a NACK interrupt request is generated if the SDA
rising edge of the 9th bit of transmit clock pulse. An ACK interrupt request is generated if the SDA
is low at the rising edge of the 9th bit of transmit clock pulse.
If ACK2 is selected for the cause of DMA1 request, a DMA transfer can be activated by detection of an
acknowledge.
If a start condition is detected while the STAC bit is set to "1" (UART2 initialization enabled), the serial
I/O operates as described below.
- The transmit shift register is initialized, and the content of the U2TB register is transferred to the
- The receive shift register is initialized, and the serial I/O starts receiving data synchronously with the
- The SWC bit is set to “1” (SCL
Note that when UART2 transmission/reception is started using this function, the TI does not change
state. Note also that when using this function, the selected transfer clock should be an external clock.
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4
transmit shift register. In this way, the serial I/O starts sending data synchronously with the next clock
when a start condition was detected until the first bit in the data is output synchronously with the input
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pulse applied. However, the UART2 output value does not change state and remains the same as
clock.
next clock pulse applied.
falling edge of the ninth clock pulse.
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page 200
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wait output enabled). Consequently, the SCL
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pin is pulled low at the
14. Serial I/O
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