C8051F040-GQ Silicon Laboratories Inc, C8051F040-GQ Datasheet - Page 154

• Manufacturer Part Number: C8051F040-GQ
• Description: IC 8051 MCU 64K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F04xr

Specifications of C8051F040-GQ

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b, 13x12b; D/A 2x10b, 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: CAN/SMBus/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F040DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 8-bit or 13-ch x 12-bit
• On-chip Dac: 2-ch x 12-bit
• No. Of I/o's: 64
• Ram Memory Size: 4352Byte
• Cpu Speed: 25MHz
• No. Of Timers: 5
• Rohs Compliant: Yes
• Data Rom Size: 64 KB
• A/d Bit Size: 12 bit
• A/d Channels Available: 13
• Height: 1 mm
• Length: 14 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Width: 14 mm
• Package: 100TQFP
• Device Core: 8051
• Family Name: C8051F04x
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1205 - DEV KIT FOR F040/F041/F042/F043
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1204

C8051F040/1/2/3/4/5/6/7
12.3.2. External Interrupts
The external interrupt sources (/INT0 and /INT1) are configurable as active-low level-sensitive or active-
low edge-sensitive inputs depending on the setting of bits IT0 (TCON.0) and IT1 (TCON.2). IE0 (TCON.1)
and IE1 (TCON.3) serve as the interrupt-pending flag for the /INT0 and /INT1 external interrupts, respec-
tively. If an /INT0 or /INT1 external interrupt is configured as edge-sensitive, the corresponding interrupt-
pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When configured
as level sensitive, the interrupt-pending flag follows the state of the external interrupt's input pin. The exter-
nal interrupt source must hold the input active until the interrupt request is recognized. It must then deacti-
vate the interrupt request before execution of the ISR completes or another interrupt request will be
generated.
154
Reset
External Interrupt 0
(/INT0)
Timer 0 Overflow
External Interrupt 1
(/INT1)
Timer 1 Overflow
UART0
Timer 2
Serial Peripheral
Interface
SMBus Interface
ADC0 Window
Comparator
Programmable
Counter Array
Comparator 0
Interrupt Source
0x0000
0x0003
0x000B
0x0013
0x001B
0x0023
0x002B
0x0033
0x003B
0x0043
0x004B
0x0053
Interrupt
Vector
Top
0
1
2
3
4
5
6
7
8
9
10
Table 12.4. Interrupt Summary
Priority
Order
None
IE0 (TCON.1)
TF0 (TCON.5)
IE1 (TCON.3)
TF1 (TCON.7)
RI0 (SCON0.0)
TI0 (SCON0.1)
TF2 (TMR2CN.7)
SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN
(SPI0CN.4)
SI (SMB0CN.3)
AD0WINT
(ADC0CN.2)
CF (PCA0CN.7)
CCFn (PCA0CN.n)
CP0FIF/CP0RIF
(CPT0CN.4/.5)
Pending Flag
Rev. 1.5
N/A N/A
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
0
0
0
0
0
0
0
0
0
0
0
1
Always
Enabled
EX0 (IE.0) PX0 (IP.0)
ET0 (IE.1) PT0 (IP.1)
EX1 (IE.2) PX1 (IP.2)
ET1 (IE.3) PT1 (IP.3)
ES0 (IE.4) PS0 (IP.4)
ET2 (IE.5) PT2 (IP.5)
ESPI0
(EIE1.0)
ESMB0
(EIE1.1)
EWADC0
(EIE1.2)
EPCA0
(EIE1.3)
CP0IE
(EIE1.4)
Enable
Flag
Always
Highest
PSPI0
(EIP1.0)
PSMB0
(EIP1.1)
PWADC0
(EIP1.2)
PPCA0
(EIP1.3)
PCP0
(EIP1.4)
Priority
Control