C8051F040-GQ Silicon Laboratories Inc, C8051F040-GQ Datasheet - Page 327

• Manufacturer Part Number: C8051F040-GQ
• Description: IC 8051 MCU 64K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F04xr

Specifications of C8051F040-GQ

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b, 13x12b; D/A 2x10b, 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: CAN/SMBus/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F040DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 8-bit or 13-ch x 12-bit
• On-chip Dac: 2-ch x 12-bit
• No. Of I/o's: 64
• Ram Memory Size: 4352Byte
• Cpu Speed: 25MHz
• No. Of Timers: 5
• Rohs Compliant: Yes
• Data Rom Size: 64 KB
• A/d Bit Size: 12 bit
• A/d Channels Available: 13
• Height: 1 mm
• Length: 14 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Width: 14 mm
• Package: 100TQFP
• Device Core: 8051
• Family Name: C8051F04x
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1205 - DEV KIT FOR F040/F041/F042/F043
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1204

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Revision 1.3 to Revision 1.4
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OCUMENT
Updated document to support C8051F044, C8051F045, C8051F046, and C8051F047.
Removed Preliminary tag.
Updated specifications in all tables.
Pinout chapter: Specified that the MONEN pin should be tied directly to V
10-Bit ADC chapter: Corrected the order on the inputs for the Figure 6.2 MUX.
ADC chapters: Added reference to minimum tracking time in the Tracking Modes section.
Comparators chapter: Changed Bit 6 of CPTnCN to Read Only.
CIP51 chapter: Updated IDLE mode and recommendations.
CIP51 chapter: Updated Interrupt behavior and EA recommendations.
CIP51 chapter: Changed “default priority order” to “low priority” for low priority descriptions in the inter-
rupt priority registers.
CIP51 chapter: Added AMX2CF to the list of SFRs in Table 12.3, “Special Function Registers,” on
page 147.
Oscillators chapter: Added example for a 32.768 kHz external crystal.
Flash chapter: Emphasized that the page containing the Lock Bytes cannot be erased from software
and writes to the Reserved Area are undefined and not recommended.
Port I/O chapter: Specified that P4-P7 are on SFR Page 0x0F.
SMBus chapter: Fixed the first equation in the SMB0CR register description.
UART0 chapter: Clarified the Baud Rate equations to allow for different timer clock sources by sepa-
rating the timer configuration and UART configuration into two equations.
UART0 chapter: Fixed transmit and receive error descriptions.
Timer 2, 3, and 4 chapter: Changed the square wave output frequency equations.
Timer 2, 3, and 4 chapter: Changed references from "TnCON" to "TMRnCN."
Timer 2, 3, and 4 chapter: Changed the TOE description in TMRnCF to indicate that C/Tn = 0.
PCA chapter: Specified that the low-byte should be written first for most PCA modes.
JTAG chapter: Added description for the SFLE bit in the JTAG FLASHCON register.
Fixed various grammar and punctuation errors.
C
HANGE
L
IST
Rev. 1.4
C8051F040/1/2/3/4/5/6/7
DD
in most applications.
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