C8051F040-GQ Silicon Laboratories Inc, C8051F040-GQ Datasheet - Page 233
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C8051F040-GQ
Manufacturer Part Number
C8051F040-GQ
Description
IC 8051 MCU 64K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Datasheets
1.C8051F040-TB.pdf
(328 pages)
2.C8051F040-TB.pdf
(2 pages)
3.C8051F043-GQ.pdf
(328 pages)
Specifications of C8051F040-GQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
100-TQFP, 100-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 13x12b; D/A 2x10b, 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
CAN/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
64
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F040DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 13-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
64
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
5
Rohs Compliant
Yes
Data Rom Size
64 KB
A/d Bit Size
12 bit
A/d Channels Available
13
Height
1 mm
Length
14 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
14 mm
Package
100TQFP
Device Core
8051
Family Name
C8051F04x
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1205 - DEV KIT FOR F040/F041/F042/F043
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1204
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F040-GQ
Manufacturer:
SiliconL
Quantity:
702
Company:
Part Number:
C8051F040-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F040-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051F040-GQR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
The following steps are performed to initialize the CAN timing registers:
18.2. CAN Registers
CAN registers are classified as follows:
1. CAN Controller Protocol Registers: CAN control, interrupt, error control, bus status, test
2. Message Object Interface Registers: Used to configure 32 Message Objects, send and
3. Message Handler Registers: These read only registers are used to provide information to
4. CIP-51 MCU Special Function Registers (SFR): Six registers located in the CIP-51 MCU
18.2.1. CAN Controller Protocol Registers
The CAN Control Protocol Registers are used to configure the CAN controller, process interrupts, monitor
bus status, and place the controller in test modes. The CAN controller protocol registers are accessible
using CIP-51 MCU SFR’s by an indexed method, and some can be accessed directly by addressing the
SFR’s in the CIP-51 SFR map for convenience.
The registers are: CAN Control Register (CAN0CN), CAN Status Register (CAN0STA), CAN Test Register
(CAN0TST), Error Counter Register, Bit Timing Register, and the Baud Rate Prescaler (BRP) Extension
Register. CAN0STA, CAN0CN, and CAN0TST can be accessed via CIP-51 MCU SFR’s. All others are
accessed indirectly using the CAN address indexed method via CAN0ADR, CAN0DATH, and CAN0DATL.
Please refer to the Bosch CAN User’s Guide for information on the function and use of the CAN
Control Protocol Registers.
18.2.2. Message Object Interface Registers
There are two sets of Message Object Interface Registers used to configure the 32 Message Objects that
transmit and receive data to and from the CAN bus. Message objects can be configured for transmit or
receive, and are assigned arbitration message identifiers for acceptance filtering by all CAN nodes.
modes.
receive data to and from Message Objects. The CIP-51 MCU accesses the CAN mes-
sage RAM via the Message Object Interface Registers. Upon writing a message object
number to an IF1 or IF2 Command Request Register, the contents of the associated
Interface Registers (IF1 or IF2) will be transferred to or from the message object in CAN
RAM.
the CIP-51 MCU about the message objects (MSGVLD flags, Transmission Request
Pending, New Data Flags) and Interrupts Pending (which Message Objects have caused
an interrupt or status interrupt condition).
memory map that allow direct access to certain CAN Controller Protocol Registers, and
Indexed indirect access to all CAN registers.
Step 1. Set the SFRPAGE register to CAN0_PAGE.
Step 2. Set the INIT the CCE bits to ‘1’ in the CAN Control Register accessible through the
Step 3. Set the CAN0ADR to 0x03 to point to the Bit Timing Register.
Step 4. Write the value 0x5EC0 to the [CAN0DATH:CAN0DATL] CIP-51 SFRs to set the Bit
Step 5. Perform other CAN initializations.
CAN0CN SFR.
Timing Register using the indirect indexing method described on
234.
Rev. 1.4
C8051F040/1/2/3/4/5/6/7
Section 18.2.5 on page
233