M30260F6AGP#U5A Renesas Electronics America, M30260F6AGP#U5A Datasheet - Page 215

• Manufacturer Part Number: M30260F6AGP#U5A
• Description: IC M16C MCU FLASH 48K 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: UART
• Total Internal Ram Size: 2KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: R8C
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 39
• Number Of Timers: 8
• For Use With: R0K33026AS000BE - KIT DEV EVALUATION M16C/26A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

M
R
R
e
E
1
. v
NOTE:
J
6
Table 14.1.6.1 Simultaneous Sample Sweep Mode Specifications
Function
A/D Conversion Start Condition
A/D Conversion Stop Condition
Interrupt Generation Timing A/D conversion completed
Analog Input Pin
Readout of A/D conversion result Readout one of the AN0 to AN7 registers that corresponds to the selected pin
Figure 14.1.6.1 Operation Example in Simultaneous Sample Sweep Mode
0
C
2
9
14.1.6 Simultaneous Sample Sweep Mode
2 /
0 .
B
1. AN
In simultaneous sample sweep mode, analog voltages applied to the selected pins are converted one-by-
one to a digital code. At this time, the input voltage of AN
circuits of sample and hold circuit. Table 14.1.6.1 shows the simultaneous sample sweep mode specifica-
tions. Figure 14.1.6.1 shows the operation example in simultaneous sample sweep mode. Figure
14.1.6.2 shows ADCON0 to ADCON2 registers and Figure 14.1.6.3 shows ADTRGCON registers in
simultaneous sample sweep mode. Table 14.1.6.2 shows the trigger select bit setting in simultaneous
sample sweep mode. In simultaneous sample sweep mode, Timer B0 underflow can be selected as a
trigger by combining software trigger, AD
frequency setting counter underflow or A/D trigger mode of Timer B.
0
0
6
2
A
the same group.
0
F
2
G
e
0 -
30
b
o r
Item
AN
AN
AN
AN
AN
AN
AN
AN
1 .
2
to AN
•Example when selecting AN
u
0
, 5
0
1
2
3
4
5
6
7
0
p
2
(
A/D conversion started
0
M
0
32
1
7
6
can be used in the same way as AN
C
page 196
2 /
6
, A
M
The SCAN1 to SCAN0 bits in the ADCON1 register and ADGSEL1 to
ADGSEL0 bits in the ADCON2 register select pins. Analog voltage applied to
the selected pins is converted one-by-one to a digital code. At this time, the
input voltage of AN
When the TRG bit in the ADCON0 register is "0" (software trigger)
When the TRG bit in the ADCON0 register is "1" (hardware trigger)
A/D conversion completed (If selecting software trigger, the ADST bit is
automatically set to "0".
Set the ADST bit to "0" (A/D conversion halted)
Select from AN
AN
1
Set the ADST bit in the ADCON0 register to “1” (A/D conversion started)
The trigger is selected by TRG1 and HPTRG0 bits (See Table 14.1.6.2)
The AD
to “1” (A/D conversion started)
Timer B0, B2 or Timer B2 interrupt generation frequency setting counter
underflow after setting the ADST bit to “1” (A/D conversion started)
f o
6
C
0
3
2 /
to AN
2
0
9
to
6
, B
AN
TRG
3
7
M
to analog input pins (SCAN1 to SCAN0=01
(8 pins)
1
pin input changes state from “H” to “L” after setting the ADST bit
6
C
0
TRG
2 /
to AN
6
0
) T
(1)
trigger, Timer B2 underflow, Timer B2 interrupt generation
and AN
A/D interrupt request generated
1
(2 pins), AN
0
1
to AN
are sampled simultaneously.
0
and AN
Specification
7
. However, all input pins need to belong to
0
to AN
1
are sampled simultaneously using two
3
(4 pins), AN
2
)
A/D pin input voltage
sampling
A/D pin conversion
0
to AN
14. A/D Converter
5
(6 pins), or