MC9S12C32CFAE25 Freescale Semiconductor, MC9S12C32CFAE25 Datasheet - Page 119

• Manufacturer Part Number: MC9S12C32CFAE25
• Description: IC MCU 32K FLASH 25MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C32CFAE25

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 31
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• For Use With: CML12C32SLK - KIT STUDENT LEARNING 16BIT HCS12
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1. The RAM Reset BASE Address is based on the reset value of the INITRM register, 0x0009.
2. Alignment of the Allocated RAM space within the RAM mappable region is dependent on the value of RAMHAL.
3.3.2.8
Read: Anytime
Write: Writes have no effect
Reset: Defined at chip integration, see device overview section.
The MEMSIZ1 register reflects the state of the FLASH or ROM physical memory space and paging
switches at the core boundary which are configured at system integration. This register allows read
visibility to the state of these switches.
Freescale Semiconductor
Module Base + 0x001D
Starting address location affected by INITRG register setting.
Reset
ram_sw2:ram_sw0
W
R ROM_SW1
011
100
101
110
111
Memory Size Register 1 (MEMSIZ1)
—
7
As stated, the bits in this register provide read visibility to the system
physical memory space allocations defined at system integration. The actual
array size for any given type of memory block may differ from the allocated
size. Please refer to the device overview chapter for actual sizes.
= Unimplemented or Reserved
ROM_SW0
—
6
Table 3-9. Allocated RAM Memory Space (continued)
RAM Space
Allocated
10K bytes
12K bytes
14K bytes
16K bytes
Figure 3-10. Memory Size Register 1 (MEMSIZ1)
8K bytes
MC9S12C-Family / MC9S12GC-Family
—
0
5
Mappable Region
16K bytes
16K bytes
16K bytes
16K bytes
Rev 01.24
NOTE
8K bytes
—
0
4
RAM
Chapter 3 Module Mapping Control (MMCV4) Block Description
2
2
2
—
0
3
RAM[15:13]
RAM[15:14]
RAM[15:14]
RAM[15:14]
RAM[15:14]
Bits Used
INITRM
—
0
2
PAG_SW1
—
1
Base Address
RAM Reset
0x0000
0x1800
0x1000
0x0800
0x0000
PAG_SW0
—
0
(1)
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